SLWU079D March   2012  – April 2016

 

  1.   TSW140x High Speed Data Capture/Pattern Generator Card
    1.     Trademarks
    2. 1 Functionality
      1. 1.1 ADC EVM Data Capture
      2. 1.2 DAC EVM Pattern Generator
    3. 2 Hardware Configuration
      1. 2.1 Power Connections
        1. 2.1.1 Output Power Regulators
      2. 2.2 Switches, Jumpers and Fuses
        1. 2.2.1 Switches and Pushbuttons
        2. 2.2.2 Jumpers
        3. 2.2.3 Fuses
      3. 2.3 LEDs
      4. 2.4 Connectors
        1. 2.4.1 Input LVDS ADC Interface Connector
        2. 2.4.2 JTAG Connector
        3. 2.4.3 Input CMOS ADC Interface Connector
        4. 2.4.4 Output LVDS Connector
        5. 2.4.5 Output CMOS DAC Interface Connector
        6. 2.4.6 USB I/O Connection
    4. 3 Software Start up
      1. 3.1 Installation Instructions
      2. 3.2 USB Interface and Drivers
      3. 3.3 Device ini Files
    5. 4 ADC Data Capture Software Operation
      1. 4.1 Testing a TSW1400 EVM with an ADS5281 EVM
      2. 4.2 Testing a TSW1400EVM with an ADS62P49EVM (CMOS Interface)
    6. 5 TSW1400 Pattern Generator Operation
      1. 5.1 Testing a TSW1400 EVM with a DAC3152 EVM
      2. 5.2 Loading DAC Firmware
      3. 5.3 Configuring TSW1400 for Pattern Generation
      4. 5.4 Testing a TSW1400 EVM with a DAC5688EVM (CMOS Interface)
    7. 6 TSW1405 Functional Description
      1. 6.1 Hardware Description
        1. 6.1.1 Power Connections
        2. 6.1.2 Pushbuttons
        3. 6.1.3 Jumpers
        4. 6.1.4 LEDs
      2. 6.2 Software Operation
        1. 6.2.1 Channel Selection
    8. 7 TSW1406 Functional Description
      1. 7.1 Hardware Description
        1. 7.1.1 Power Connections
        2. 7.1.2 Pushbuttons
        3. 7.1.3 Jumpers
        4. 7.1.4 LEDs
      2. 7.2 Software Operation
    9. 8 Revision History

2.2.2 Jumpers

Jumpers JP5, JP6, and JP7 allow the option to break the connection on three GPIO signals that are routed between connector J3 and USB controller U3 through buffer U16. When the jumper shunts are removed and buffer U16 is disabled, the user can provided external signals to three signals going to an ADC EVM that is connected to J3 by using pin 1 of JP5, JP6, and JP7. Connecting pins 1 and 2 of Jumper SJP1 will disable U16. Connecting pins 1 and 2 of Jumper SJP2 will disable U17, which is the buffer providing the GPIO signals to the DAC EVM interface connector. See the TSW1400 EVM schematic for more details.

Jumpers JP3 and JP4 set the output voltage of buffers U16 and U17. These buffers provide GPIO signals between the TSW1400 and ADC and DAC EVMs. When set to pins 1-2, the buffers will provide 1.8-V CMOS logic level signal interface to the ADC and DAC EVM connectors. When set to 2-3, the level will be 3 V. JP3 controls the ADC signals, and JP4 controls the DAC signals. See the TSW1400 EVM schematic for more details.

Jumper JP8 sets the signal output voltage of CMOS_PORT1[19:1] bus on connector J1. When set to pins 1-2, the FPGA will provide 1.8-V CMOS logic level signals. When set to 2-3, the level will be 3 V.