SLAZ742A July   2023  – October 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3106 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3506 , MSPM0G3507 , MSPM0G3507-Q1

 

  1.   1
  2.   Abstract
  3. 1Functional Advisories
  4. 2Preprogrammed Software Advisories
  5. 3Debug Only Advisories
  6. 4Fixed by Compiler Advisories
  7. 5Device Nomenclature
  8. 6Advisory Descriptions
    1. 6.1  ADC_ERR_01
    2. 6.2  ADC_ERR_02
    3. 6.3  BSL_ERR_01
    4. 6.4  COMP_ERR_02
    5. 6.5  COMP_ERR_03
    6. 6.6  CPU_ERR_01
    7. 6.7  GPIO_ERR_01
    8. 6.8  I2C_ERR_01
    9. 6.9  I2C_ERR_02
    10. 6.10 I2C_ERR_03
    11. 6.11 PWREN_ERR_01
    12. 6.12 RTC_ERR_01
    13. 6.13 SPI_ERR_01
    14. 6.14 SPI_ERR_02
    15. 6.15 SYSOSC_ERR_01
    16. 6.16 TIMER_ERR_01
    17. 6.17 VREF_ERR_01
    18. 6.18 WWDT_ERR_01
    19. 6.19 WWDT_ERR_02
  9. 7Revision History

6.15 SYSOSC_ERR_01

MFCLK may drift when using SYSOSC FCL mode and STOP1

Revisions Affected

B

Details

IF MFCLK is enabled AND SYSOSC is using the frequency correction loop (FCL) mode AND the STOP1 low power operating mode is used, THEN the MFCLK may drift by two cycles when SYSOSC shifts from 4MHz back to 32MHz (either upon exit from STOP1 to RUN mode or upon an asynchronous fast clock request that forces SYSOSC to 32MHz).

Workaround

Use STOP0 mode instead of STOP1 mode. There is no MFCLK drift when STOP0 mode is used.

OR

Do not use SYSOSC in the FCL mode (leave FCL disabled) when using STOP1.