SLAZ742A July   2023  – October 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3106 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3506 , MSPM0G3507 , MSPM0G3507-Q1

 

  1.   1
  2.   Abstract
  3. 1Functional Advisories
  4. 2Preprogrammed Software Advisories
  5. 3Debug Only Advisories
  6. 4Fixed by Compiler Advisories
  7. 5Device Nomenclature
  8. 6Advisory Descriptions
    1. 6.1  ADC_ERR_01
    2. 6.2  ADC_ERR_02
    3. 6.3  BSL_ERR_01
    4. 6.4  COMP_ERR_02
    5. 6.5  COMP_ERR_03
    6. 6.6  CPU_ERR_01
    7. 6.7  GPIO_ERR_01
    8. 6.8  I2C_ERR_01
    9. 6.9  I2C_ERR_02
    10. 6.10 I2C_ERR_03
    11. 6.11 PWREN_ERR_01
    12. 6.12 RTC_ERR_01
    13. 6.13 SPI_ERR_01
    14. 6.14 SPI_ERR_02
    15. 6.15 SYSOSC_ERR_01
    16. 6.16 TIMER_ERR_01
    17. 6.17 VREF_ERR_01
    18. 6.18 WWDT_ERR_01
    19. 6.19 WWDT_ERR_02
  9. 7Revision History

6.11 PWREN_ERR_01

Peripheral registers are still accessible after disabling PWREN register

Revisions Affected

B

Details

When disabling the power of a peripheral by setting the PWREN register to 0, the peripherals registers may appear to retain data values if read. Reading or writing to the registers when PWREN is 0 has no affect as the peripheral has no effect.

The following peripherals are affected: comparator (COMP), operational amplifier (OPA), TimerA, TimerG, general-purpose input/output (GPIO), and windowed watchdog timer (WWDT), AES and TRNG.

Workaround

When the PWREN register of the peripheral is set to 0, the values of the associated registers should be disregarded or considered invalid.