SLAAEP0 March   2026 TAA5212 , TAA5412-Q1 , TAC5111 , TAC5111-Q1 , TAC5112 , TAC5112-Q1 , TAC5211 , TAC5212 , TAC5301-Q1 , TAC5311-Q1 , TAC5312-Q1 , TAC5412-Q1 , TAD5112 , TAD5112-Q1 , TAD5212 , TAD5212-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Clock Tree
  6. 3Clocking Limits
    1. 3.1 Internal Frequency Ranges
    2. 3.2 Clock Divider Parameter Ranges
    3. 3.3 Clock Enable Registers
  7. 4Manual Clock Tree Configuration Registers
    1. 4.1 Required Register Settings
    2. 4.2 Register Settings in Manual Clock Tree Configuration
    3. 4.3 Sample Rate and MOD_CLK Frequency Bins
    4. 4.4 Power Consumption Considerations
  8. 5Calculating PLL Multiplier and Dividers
  9. 6Example 1: Custom Target Mode, Non-Audio Rates
    1. 6.1 Example Script
  10. 7Example 2: Custom Controller Mode, Non-Audio Rates
    1. 7.1 Example Script
  11. 8Summary
  12. 9References

Sample Rate and MOD_CLK Frequency Bins

The frequency of MOD_CLK changes with the sample rate, also called FS. The TAx5x1x devices have many defined sample rate frequency bins, with the center frequency of the bin being the expected frequency that would allow the MOD_CLK to be either 3.072MHz or 1.536MHz. The sample rate relates to the MOD_CLK by an integer multiple called the oversampling rate (OSR).

Table 4-3 shows all the possible bins in the device, along with the OSR. The Bin ID is used in register P0_R50 and P0_R51 when specifying the sample rate, with the decimal value of the bin in bits 7-2. These are the same bins used for semi-automatic mode. In manual mode, pay special attention to the OSR associated with each bin. Sample rates can be any value between the minimum and maximum FS shown for each bin, and some frequencies may fall into multiple bins. For these scenarios, choose the bin with the typical value that is closest to the desired sample rate for best performance.

There are two options for the internal MOD_CLK, which affects the oversampling rate of the delta-sigma ADC/DAC. More about the considerations of the options is in Section 4.4.

Table 4-3 Mod Clock and Sample Rate Frequency Bins
MOD_CLK=3.072MHz ModeMOD_CLK=1.536MHz Mode
Bin IDOSRMin FSTypical FSMax FSBin IDOSRMin FSTypical FSMax FS
1467032076800080640012670320768000806400
25536256614400645120Not supported
3644688051200053760033446880512000537600
47383040438857.143460800Not supported
5833516038400040320054335160384000403200
69297920341333.333358400Not supported
71026812830720032256075268128307200322560
81222344025600026880086223440256000268800
914191520219428.57123040097191520219428.571230400
1016167580192000201600108167580192000201600
1118148960170666.667179200119148960170666.667179200
12201340641536001612801210134064153600161280
13241117201280001344001312111720128000134400
142895760109714.286115200141495760109714.286115200
1532837909600010080015168379096000100800
16367448085333.3338960016187448085333.33389600
17406703276800806401720670327680080640
18485586064000672001824558606400067200
19564788054857.14295760019284788054857.142957600
20644189548000504002032418954800050400
21723724042666.6674480021363724042666.66744800
22803351638400403202240335163840040320
23962793032000336002348279303200033600
241122394027428.57142880024562394027428.571428800
2512820947.52400025200256420947.52400025200
261441862021333.3332240026721862021333.33322400
271601675819200201602780167581920020160
281921396516000168002896139651600016800
292241197013714.285714400291121197013714.285714400
3025610473.7512000126003012810473.751200012600
31288931010666.6671120031144931010666.66711200
323208379960010080321608379960010080
333846982.580008400331926982.580008400
3444859856857.1428672003422459856857.142867200
355125236.87560006300352565236.87560006300
3628846555333.3335600
373204189.548005040
383843491.2540004200
394482992.53428.57143600
405122618.43830003150