When selecting internal clocks, note the relationships between speed, power consumption, and processing cycles. As the internal clocks run faster, the power consumption increases. However, the amount of cycles per sample increases, allowing internal processing to increase such as using more biquad filters, more channels, or lower group delay decimation/interpolation filters. The internal clocks to pay attention to for these considerations include the input to the PLL, since PLL in integer mode uses less power than in fractional mode, the PLL multiplier creating CLK_SYS, and the relationship between MOD_CLK and DEM_CLK. By default, DEM_CLK will be 4x the MOD_CLK, but it can be forced to be 2x in the PWR_TUNE configuration registers. This will reduce the current consumption slightly, as shown in the application notes TAC5x1x Power Consumption Matrix Across Various Usage Scenarios, TAA52xx Power Consumption Matrix Across Various Usage Scenarios, and TAD52xx Power Consumption Matrix Across Various Usage Scenarios. However, this is not recommended to be changed except in extreme power-saving configurations. The MOD_CLK has two speed options to select from, and the same considerations can be taken for this. A higher internal MOD_CLK is generally preferred, since this allows the most internal cycles per sample which is best for allowing maximal DSP processing, but sometimes the lower MOD_CLK rate is needed for especially low sample rates or for low power applications, or if the internal clocking math requires this lower rate. This math is explained in Section 5.