# Controller mode, 16 bit 2 channel TDM, wide bandwidth mode, MOD_CLK=1.5MHz mode
# CCLK in=50MHz, WCLK out=98kHz, BCLK out=3.136MHz
# CCLK on GPIO1

w a0 00 00 #Set page 0
w a0 01 01 #Software Reset
w a0 02 09 #Wake up with AVDD > 2v and all VDDIO level
w a0 0a 10 #configure GPIO1 as input
w a0 0f 20 #Set GPIO1=CCLK
w a0 1a 00 #PASI TDM, 16 bit format
w a0 1e 20 #PASI DOUT Ch1 on TDM slot 0
w a0 1f 21 #PASI DOUT Ch2 on TDM slot 1
w a0 28 20 #PASI DIN Ch1 on TDM slot 0
w a0 29 21 #PASI DIN Ch2 on TDM slot 1
w a0 32 3f #FS bin=15, 5% tolerance, custom clock configuration
w a0 34 48 #PLL enabled, fraction mode enabled, fixed CCLK is input clock source
w a0 37 30 #PASI in controller configuration
w a0 38 80 #use internal BCLK for FSYNC generation
w a0 39 20 #LSB for pasi BCLK to FSYNC ratio = 32d
w a0 4e 80 #ADC MOD_CLK = 1.5mhz
w a0 4f 80 #DAC MOD_CLK = 1.5mhz

w a0 00 03 #page 3
w a0 32 80 #PLL_PDIV_IN_CLK is CCLK, and PASI BCLK divider source is PLL output
w a0 34 10 #(default) NM div input clock is PLL output
w a0 35 04 #PDIV=4
w a0 36 14 #J MSB=0, D MSB=01 0100 (D=5264)
w a0 37 90 #D LSB= 1001 0000
w a0 38 07 #J LSB=00000111 (J=7)
w a0 39 20 #NDIV=1, PDM_DIV=1
w a0 3a 3e #MDIV=15, DIG_ADC_MODCLK_DIV=4
w a0 3b 28 #DIG_DAC_MODCLK_DIV=4, DAC MOD_CLK 2x disabled (1.536 mode)
w a0 3c 1e #PASI BCLK divider=30
w a0 3e 0f #ANA_NM_DIV=15
w a0 44 07 #NDIV, MDIV, and PDMDIV enabled
w a0 45 fa #MODCLK, PASI BDIV, and PASI FSYNC DIV enabled

w a0 00 00 #page 0
w a0 50 01 #ADC Ch1 diff input, 5KOhm, 2Vrms AC-coupled, wide band mode (over 96k)
w a0 55 01 #ADC Ch2 diff input, 5KOhm, 2Vrms ac-coupled, wide band mode (over 96k)
w a0 65 21 #OUT1P LINEOUT 0dB, DAC ch1 wide band mode (over 96k)
w a0 6c 21 #OUT2P LINEOUT 0dB, DAC ch2 wide band mode (over 96k
w a0 76 cc #enable input and output channels 1 and 2
w a0 78 e0 #Power up all DAC+ADC channels