SLAAEP0 March   2026 TAA5212 , TAA5412-Q1 , TAC5111 , TAC5111-Q1 , TAC5112 , TAC5112-Q1 , TAC5211 , TAC5212 , TAC5301-Q1 , TAC5311-Q1 , TAC5312-Q1 , TAC5412-Q1 , TAD5112 , TAD5112-Q1 , TAD5212 , TAD5212-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Clock Tree
  6. 3Clocking Limits
    1. 3.1 Internal Frequency Ranges
    2. 3.2 Clock Divider Parameter Ranges
    3. 3.3 Clock Enable Registers
  7. 4Manual Clock Tree Configuration Registers
    1. 4.1 Required Register Settings
    2. 4.2 Register Settings in Manual Clock Tree Configuration
    3. 4.3 Sample Rate and MOD_CLK Frequency Bins
    4. 4.4 Power Consumption Considerations
  8. 5Calculating PLL Multiplier and Dividers
  9. 6Example 1: Custom Target Mode, Non-Audio Rates
    1. 6.1 Example Script
  10. 7Example 2: Custom Controller Mode, Non-Audio Rates
    1. 7.1 Example Script
  11. 8Summary
  12. 9References

4.1 Required Register Settings

To enable manual clock configuration on the TAx5x1x devices, these registers must be set. Then, all other desired clock divider registers can be set.

Table 4-1 Required Register Settings to Enable Operation in Manual Clock Config
I2C BitsRegister Setting
CUSTOM_CLK_CFG (B0_P0)0x32[0] must be 1b
PASI_SAMP_RATE (B0_P0)0x32[7:2] set according to Table 4-3
SASI_SAMP_RATE (B0_P0)0x32[7:2] set according to Table 4-3if secondary ASI is desired
CLK_CFG30 (B0_P3)0x44[1] set to 1 to enable MDIV, other dividers enable if used
CLK_CFG31 (B0_P3)0x45[7:4] set to 1 to enable internal clocks for ADC/DAC operation, other dividers enable if used