SLAAEP0 March   2026 TAA5212 , TAA5412-Q1 , TAC5111 , TAC5111-Q1 , TAC5112 , TAC5112-Q1 , TAC5211 , TAC5212 , TAC5301-Q1 , TAC5311-Q1 , TAC5312-Q1 , TAC5412-Q1 , TAD5112 , TAD5112-Q1 , TAD5212 , TAD5212-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Clock Tree
  6. 3Clocking Limits
    1. 3.1 Internal Frequency Ranges
    2. 3.2 Clock Divider Parameter Ranges
    3. 3.3 Clock Enable Registers
  7. 4Manual Clock Tree Configuration Registers
    1. 4.1 Required Register Settings
    2. 4.2 Register Settings in Manual Clock Tree Configuration
    3. 4.3 Sample Rate and MOD_CLK Frequency Bins
    4. 4.4 Power Consumption Considerations
  8. 5Calculating PLL Multiplier and Dividers
  9. 6Example 1: Custom Target Mode, Non-Audio Rates
    1. 6.1 Example Script
  10. 7Example 2: Custom Controller Mode, Non-Audio Rates
    1. 7.1 Example Script
  11. 8Summary
  12. 9References

1 Introduction

The TAx5x1x devices support a few automatic modes of PLL configuration, where the internal clocks get configured based on input clocks (CCLK, BCLK, FSYNC). While the automatic modes for this family of devices can cover most typical use cases, there are times when manual clocking is needed or preferred. Some example use cases of manual clocking include:

  1. When in controller mode and CCLK has no integer relation with FSYNC frequency, and is not one of the allowed CCLK frequencies for auto CCLK fixed mode found in Table 3-7 of Clocking Configuration of Device and Flexible Clocking For TAx5x1x Family.
    1. For example, 15MHz CCLK and 48kHz FSYNC.
  2. Non-standard sample rate with specific clocking needs. Automatic mode sample rate detection will work only for specific ranges of WCLK frequency, and semi-automatic mode will work for any supported sample rate, but you lose knowledge of the internal clocks.
    1. For example, if a user wants to use a sample rate of 50kHz (is supported in semi-automatic mode, not automatic mode) and specify what frequency of PDM clock, CLKOUT, or verify the PLL is turned on or off.
  3. Sample rate conversion at non-standard sample rates, including PASI and SASI at different rates, or one in controller and one in target mode. See TAx5x1x Synchronous Sample Rate Conversion for more information.
  4. Any other situation that requires intimate knowledge of internal clocking schemes on the TAx5x1x. Knowing internal clocks is beneficial to generate a general CLKOUT, PDM clock, or to be able to recreate settings for uniform power consumption between chips.