SLAAEP0 March   2026 TAA5212 , TAA5412-Q1 , TAC5111 , TAC5111-Q1 , TAC5112 , TAC5112-Q1 , TAC5211 , TAC5212 , TAC5301-Q1 , TAC5311-Q1 , TAC5312-Q1 , TAC5412-Q1 , TAD5112 , TAD5112-Q1 , TAD5212 , TAD5212-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Clock Tree
  6. 3Clocking Limits
    1. 3.1 Internal Frequency Ranges
    2. 3.2 Clock Divider Parameter Ranges
    3. 3.3 Clock Enable Registers
  7. 4Manual Clock Tree Configuration Registers
    1. 4.1 Required Register Settings
    2. 4.2 Register Settings in Manual Clock Tree Configuration
    3. 4.3 Sample Rate and MOD_CLK Frequency Bins
    4. 4.4 Power Consumption Considerations
  8. 5Calculating PLL Multiplier and Dividers
  9. 6Example 1: Custom Target Mode, Non-Audio Rates
    1. 6.1 Example Script
  10. 7Example 2: Custom Controller Mode, Non-Audio Rates
    1. 7.1 Example Script
  11. 8Summary
  12. 9References

3.2 Clock Divider Parameter Ranges

Table 3-4 Clock Divider Parameter Ranges
Parameter Range Register (all page 3)
J 1-511 0x36, 0x38
D 0-9999 0x36, 0x37
PDIV 1-256 0x35
NDIV 1-8 0x39
PDM_DIV 1, 2, 4, 8, 16 0x39
MDIV 1-64 0x3A
DIG_ADC_MODCLK_DIV 1, 2, 4 0x3A
DIG_DAC_MODCLK_DIV 1, 2, 4 0x3B
PASI BDIV 1-512 0x3B, 0x3C
SASI BDIV 1-512 0x3B, 0x3D
ANA_NM_DIV 1-64 0x3E
CLKOUT_DIV 1-128 0x47
BOOST_DIV 1, 2, 4, 8 0x48 (TAx53xx, TAx54xx only)
SAR_DIV 1, 2, 4, 8 0x49 (TAx53xx, TAx54xx only)