SLAAEP0 March   2026 TAA5212 , TAA5412-Q1 , TAC5111 , TAC5111-Q1 , TAC5112 , TAC5112-Q1 , TAC5211 , TAC5212 , TAC5301-Q1 , TAC5311-Q1 , TAC5312-Q1 , TAC5412-Q1 , TAD5112 , TAD5112-Q1 , TAD5212 , TAD5212-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Clock Tree
  6. 3Clocking Limits
    1. 3.1 Internal Frequency Ranges
    2. 3.2 Clock Divider Parameter Ranges
    3. 3.3 Clock Enable Registers
  7. 4Manual Clock Tree Configuration Registers
    1. 4.1 Required Register Settings
    2. 4.2 Register Settings in Manual Clock Tree Configuration
    3. 4.3 Sample Rate and MOD_CLK Frequency Bins
    4. 4.4 Power Consumption Considerations
  8. 5Calculating PLL Multiplier and Dividers
  9. 6Example 1: Custom Target Mode, Non-Audio Rates
    1. 6.1 Example Script
  10. 7Example 2: Custom Controller Mode, Non-Audio Rates
    1. 7.1 Example Script
  11. 8Summary
  12. 9References

3.3 Clock Enable Registers

Table 3-5 Clock Enable Registers
Parameter Register (page 3) Bit
NDIV_EN 0x44 2
MDIV_EN 0x44 1
PDM_DIV_EN 0x44 0
DIG_ADC_MODCLK_DIV_EN 0x45 6
DIG_DAC_MODCLK_DIV_EN 0x45 4
PASI_BDIV_EN 0x45 3
SASI_BDIV_EN 0x45 2
PASI_FSYNC_DIV_EN 0x45 1
SASI_FSYNC_DIV_EN 0x45 0
CLKOUT_DIV_EN 0x47 7
BST_CLK_MANUAL_EN 0x48 2
SAR_CLK_MANUAL_EN 0x49 2