SLAAEP0 March 2026 TAA5212 , TAA5412-Q1 , TAC5111 , TAC5111-Q1 , TAC5112 , TAC5112-Q1 , TAC5211 , TAC5212 , TAC5301-Q1 , TAC5311-Q1 , TAC5312-Q1 , TAC5412-Q1 , TAD5112 , TAD5112-Q1 , TAD5212 , TAD5212-Q1
The TAx5x1x family of devices has a flexible PLL and clock tree that can support a wide range of input and output clocking frequencies. For standard audio rates of WCLK, BCLK, and CCLK, the device can automatically configure the clock tree for performance, but if more control or non-standard audio rates are desired, the user can customize the clocking configuration as needed. The manual clocking mode involves manually setting all clock dividers and PLL parameters and can be used for both target (all ASI clocks provided externally) and controller mode (CCLK or BCLK provided, BCLK and/or WCLK generated by device). This app note serves to make the calculations of PLL parameters and clock dividers more straightforward.
This application note focuses on custom mode, and more about the automatic modes can be found in Clocking Configuration of Device and Flexible Clocking For TAx5x1x Family as well as Clock Error Configuration, Detection, and Modes Supported in TAx5x1x Family.
The clocking configuration described in this application note is available for the following devices:
TAC5111, TAC5111-Q1, TAC5112, TAC5112-Q1, TAC5211, TAC5212, TAC5212-Q1, TAC5301-Q1, TAC5311-Q1, TAC5312-Q1, TAC5411-Q1, TAC5412-Q1, TAD5112, TAD5112-Q1, TAA5212, TAD5212, TAD5212-Q1, TAA5412-Q1