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  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Board Design and Layout Guidance
    1. 2.1 General Board Design Guidance
    2. 2.2 Board Design Guidelines to Follow for Improved Signal Integrity
    3. 2.3 Description of Custom Board Design Simulations Example
  6. 3Custom Board Design Simulations
    1. 3.1 Extraction of Board Model
      1. 3.1.1 Simulations Using IBIS Model and Extracted Board Model
    2. 3.2 Simulation Setup
  7. 4Custom Board Design Examples with Circuit and Examples
    1. 4.1 Simulation Terminologies
    2. 4.2 OSPI Interface Simulation Examples for Different Use Cases
    3. 4.3 RGMII Interface Simulation Examples for Transmit Data Signals with Different Use Cases
  8. 5Summary
  9. 6References
  10. 7Revision History

2.2 Board Design Guidelines to Follow for Improved Signal Integrity

There are a number of factors that contribute to signal integrity related issues. System level analysis and optimization is recommended for improving custom board level signal integrity.

A number of options can be considered to improve custom board signal integrity (signal quality). Some of the suggested options are listed below.

Table 2-1 Signal Quality Improvement Approach Options
Options Recommendation How does the recommendation help?
A Add a series resistor Can reduce signal reflections and improve signal quality
B Add a capacitor (near to the load) Can reduce the return signal reflections. Balancing capacitors added on both ends can reduce the overall reflections.
C Increase signal trace length Can reduce out of phase reflections from impacting the incident signal while the signal is continuing to transition.
D Configure fast drive strength and use a combination of A, B, C Improves signal rise/fall time and improves overall eye pattern (along with a combination of A, B, C to reduce signal reflections).

The following diagrams are a general guidance for signal integrity improvement:

Series Resistor Added on the Data Lines Figure 2-1 Series Resistor Added on the Data Lines
Load Capacitor Added on the Clock Line Figure 2-2 Load Capacitor Added on the Clock Line
Combination of Option A and Option B on the Data Lines Figure 2-3 Combination of Option A and Option B on the Data Lines

Notes on setup and measurement:

  • Processor and Attached device (also called device) IBIS models used
  • .SNP file (extracted from the custom board using extraction tool to perform SI simulation)
  • Signal integrity analysis tool (2.5D)
  • Eye plotting tool

Note:

The eye diagrams shown in the examples have been measured at the BGA PAD of the attached device and plotted.

The analysis and examples shown are for write operations. The same guidelines can be used for simulating read operations.