SBVA093 December   2022 LP2992 , TPS786 , TPS7A30 , TPS7A3001-EP , TPS7A33 , TPS7A39 , TPS7A4501-SP , TPS7A47 , TPS7A47-Q1 , TPS7A4701-EP , TPS7A49 , TPS7A52 , TPS7A52-Q1 , TPS7A53 , TPS7A53-Q1 , TPS7A53A-Q1 , TPS7A53B , TPS7A54 , TPS7A54-Q1 , TPS7A57 , TPS7A7100 , TPS7A7200 , TPS7A7300 , TPS7A80 , TPS7A8300 , TPS7A83A , TPS7A84 , TPS7A84A , TPS7A85 , TPS7A85A , TPS7A87 , TPS7A89 , TPS7A90 , TPS7A91 , TPS7A92 , TPS7A94 , TPS7A96 , TPS7B7702-Q1 , TPS7H1111-SEP , TPS7H1111-SP , TPS7H1210-SEP

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Comprehensive Review of Error in LDO's
    1. 2.1 Commentary on Real World Error Voltage (VE) in Single LDO's
      1. 2.1.1 VREF Pin
      2. 2.1.2 VFB Pin
  5. 3Current Sharing and Load Voltage Analysis for n Parallel LDO's
    1. 3.1 Commentary on Parallel LDO's in Real World Applications
  6. 4Ballast Resistor Design and Analysis
    1. 4.1 Selecting the Ballast Resistor Value
    2. 4.2 PCB Ballast Resistor Design vs. Discrete Ballast Resistance
  7. 5Impacts and Opportunities of PCB Parasitic Impedance
  8. 6Design Examples
    1. 6.1 TPS7A57
    2. 6.2 TPS7A47xx
  9. 7Conclusion
  10. 8References

3.1 Commentary on Parallel LDO's in Real World Applications

Upon review of Equation 4 and Equation 5, there are no theoretical limitations on the number of LDO's that can be paralleled. Also, there is no assumption that all of the LDO's or output voltages must be the same. To simplify implementation, it may be advantageous to reduce variability by selecting the same LDO with the same nominal output voltage. The worst-case current sharing of each LDO can be obtained and is a function of the error voltage and ballast resistance chosen. As discussed in Section 2, the sources of variability for single LDO's are located on the VREF node and VFB node.

When the designer has access to the VREF node, they can short all VREF nodes together, providing an identical reference voltage for each device. The reference voltage is typically the dominant source of variability in steady state analysis, so connecting the reference voltage nodes together can make a significant improvement in the current sharing of each parallel LDO. With the references shorted we can simplify Equation 7 and Equation 8 for our current sharing analysis.

Equation 7. ∆VE=VREF+∆VOS∆R1+∆R2∆R2-VOUT_IDEAL+∆IBIAS∆RFBx
Equation 8. ∆VE=∆VOS

The feedback for each LDO must be before the ballast resistors and not directly on the load voltage VLOAD. Thus, we cannot tie the VFB nodes together to eliminate its contribution to VE. When selecting parallel LDO's without unity gain feedback, it is desired to minimize ∆IBIAS (listed in the LDO data sheet) or its effects on accuracy by choosing the proper feedback resistance.