SBVA093 December   2022 LP2992 , TPS786 , TPS7A30 , TPS7A3001-EP , TPS7A33 , TPS7A39 , TPS7A4501-SP , TPS7A47 , TPS7A47-Q1 , TPS7A4701-EP , TPS7A49 , TPS7A52 , TPS7A52-Q1 , TPS7A53 , TPS7A53-Q1 , TPS7A53A-Q1 , TPS7A53B , TPS7A54 , TPS7A54-Q1 , TPS7A57 , TPS7A7100 , TPS7A7200 , TPS7A7300 , TPS7A80 , TPS7A8300 , TPS7A83A , TPS7A84 , TPS7A84A , TPS7A85 , TPS7A85A , TPS7A87 , TPS7A89 , TPS7A90 , TPS7A91 , TPS7A92 , TPS7A94 , TPS7A96 , TPS7B7702-Q1 , TPS7H1111-SEP , TPS7H1111-SP , TPS7H1210-SEP

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Comprehensive Review of Error in LDO's
    1. 2.1 Commentary on Real World Error Voltage (VE) in Single LDO's
      1. 2.1.1 VREF Pin
      2. 2.1.2 VFB Pin
  5. 3Current Sharing and Load Voltage Analysis for n Parallel LDO's
    1. 3.1 Commentary on Parallel LDO's in Real World Applications
  6. 4Ballast Resistor Design and Analysis
    1. 4.1 Selecting the Ballast Resistor Value
    2. 4.2 PCB Ballast Resistor Design vs. Discrete Ballast Resistance
  7. 5Impacts and Opportunities of PCB Parasitic Impedance
  8. 6Design Examples
    1. 6.1 TPS7A57
    2. 6.2 TPS7A47xx
  9. 7Conclusion
  10. 8References

1 Introduction

Paralleling LDO’s using ballast resistors have been discussed in the industry for many years. Previously, the analysis techniques that had been developed were limited to two parallel LDO’s and did not take into consideration nonideal parasitic effects such as PCB impedance. Design and analysis of ballast resistance has not previously been fully explored, forcing the practicing engineer to use look up tables or common values such as 20 mΩ seen in many reference designs. Unfortunately, these look up tables give no methods to calculate how these ballast resistance values impact the load voltage and could be overdesigned leading to degraded performance.

Modern systems require parallel LDO designs to meet more than just additional load current or spread the heat generated by the power dissipation of the LDOs. Methods to accurately design with more than two parallel LDO’s needed to be developed as many engineers want to use 5-10 parallel LDO’s to meet their load current requirements. The voltage at the load must be calculated to ensure it meets the system requirement. This technical white paper provides a new mathematical foundation to calculate the load current and load voltage for any number of parallel LDOs. From this, we can support a new generation of designs which may parallel any number of LDO’s to meet the system load voltage and load current while optimizing the ballast resistance to include the parasitic PCB impedance for maximum performance.