SBAU171D May   2010  – January 2016 ADS1198 , ADS1298

 

  1.   ADS1298ECG-FE/ADS1198ECG-FE
    1.     Trademarks
    2. 1 ADS1298ECG-FE/ADS1198ECG-FE Overview
      1. 1.1 Important Disclaimer Information
      2. 1.2 Introduction
      3. 1.3 Supported Features
      4. 1.4 Features Not Supported in Current Version
      5. 1.5 ADS1x98ECG-FE Hardware
      6. 1.6 Minimum System Requirements for ADS1x98ECG-FE Evaluation Software
    3. 2 Quick Start
      1. 2.1 Default Jumper/Switch Configuration
      2. 2.2 ADS1x98ECG-FE Operation
    4. 3 Using the ADS1298ECG-FE Software
      1. 3.1 Application User Menu
      2. 3.2 Top-Level Application Controls
      3. 3.3 About Tab
      4. 3.4 ADC Register Tab
        1. 3.4.1 Standby and Reset Controls
        2. 3.4.2 Channel Registers Tab (ADC Register)
          1. 3.4.2.1 Global Channel Registers
          2. 3.4.2.2 Channel Control Registers
        3. 3.4.3 LOFF and RLD Tab (ADC Register)
          1. 3.4.3.1 Lead-Off Detection and Current Direction Control Registers
          2. 3.4.3.2 Right Leg Drive Derivation Control Registers
        4. 3.4.4 GPIO and OTHER Registers Tab (ADC Register)
          1. 3.4.4.1 Wilson Central and Augmented Lead Registers
        5. 3.4.5 Register Map (ADC Register)
      5. 3.5 Analysis Tab
        1. 3.5.1 Scope Tab (Anaysis)
          1. 3.5.1.1 Zoom Tool
        2. 3.5.2 Histogram Tab (Analysis)
        3. 3.5.3 FFT Tab
        4. 3.5.4 ECG Tab (Analysis)
      6. 3.6 Save Tab
    5. 4 ADS1x98ECG-FE Input Signals
      1. 4.1 Input Short Testing
      2. 4.2 Internal Test Signals Input
      3. 4.3 Temperature Sensor
      4. 4.4 Normal Electrode Input
        1. 4.4.1 Capturing 12-Lead ECG Signals
      5. 4.5 MVDD Input, RLD Measurement, RLD Positive Electrode Driver, and RLD Negative Electrode Driver
      6. 4.6 Lead Derivation
      7. 4.7 Wilson Center Terminal (WCT)
      8. 4.8 Right Leg Drive
        1. 4.8.1 RLD Common Mode Voltage
        2. 4.8.2 Driving the RLD Cable Shield
      9. 4.9 PACE Detection
    6. 5 ADS1298ECG-FE/ADS1198ECG-FE Hardware Details
      1. 5.1 Jumper Description
      2. 5.2 Power Supply
      3. 5.3 Clock
      4. 5.4 Reference
      5. 5.5 Analog Output Signals
      6. 5.6 Digital Signals
      7. 5.7 Analog Input Signals
        1. 5.7.1 Patient Simulator Input
        2. 5.7.2 Arbitrary Input Signals
  2. ASchematics, BOM, Layout, and ECG Cable Details
    1. A.1 Overview
    2. A.2 ADS1x98ECG-FE Front-End Board Schematics
    3. A.3 Bill of Materials
      1. Table 13. Bill of Materials: ADS1x98ECG-FE
    4. A.4 Printed Circuit Board Layout
    5. A.5 ECG Cable Details
  3. BExternal Optional Hardware
    1. B.1 Optional External Hardware (Not Included)
    2. B.2 ADS1x98ECG-FE Power-Supply Recommendations
  4. CSoftware Installation
    1. C.1 Minimum Requirements
    2. C.2 Installing the Software

4.8.1 RLD Common Mode Voltage

The RLD common mode voltage can be set to (AVDD+AVSS)/2 or to an externally provided source. If the application requires the common mode to be set to any voltage other than mid-supply, this can be accomplished by setting the appropriate bit in the Configuration 3 Register. On the ADS1298ECG-FE, the external RLDREF voltage is set using resistor R1 and adjustable resistor R2 (R1 and R2 are not installed by default).

During power-up, the firmware configures the device for internal RLDREF operation. To configure the RLD circuitry manually, use the following steps and the controls found on the ADC Register tab.

  1. Verify that the Channel Input is set to the Normal Electrode mode for all channels (Channel Registers tab).
  2. In CONFIG3 control register (Channel Registers tab):
    • Enable the RLD Buffer (RLD Buffer Power = Enable)
    • Set the internal RLD reference (RLDREF Signal Source)
  3. Select the electrodes for the RLD loop from the Right Leg Drive Derivation Control Registers controls (LOFF and RLD tab)

Once these steps are completed, measure and verify that the voltage on either side of R38 is close to mid-supply. This measurement confirms whether the RLD loop is functional.

The on-chip RLD signal can be fed back into the ADS1298 by shorting JP1. This RLD signal can then be sent to the ADC (to measure for debug purposes) or to other electrodes for driving (to change the reference drive in case the RL electrode falls off). Refer to the ADS1298 product data sheet or ADS1198 data sheet for additional details.