SBAU171D May   2010  – January 2016 ADS1198 , ADS1298

 

  1.   ADS1298ECG-FE/ADS1198ECG-FE
    1.     Trademarks
    2. 1 ADS1298ECG-FE/ADS1198ECG-FE Overview
      1. 1.1 Important Disclaimer Information
      2. 1.2 Introduction
      3. 1.3 Supported Features
      4. 1.4 Features Not Supported in Current Version
      5. 1.5 ADS1x98ECG-FE Hardware
      6. 1.6 Minimum System Requirements for ADS1x98ECG-FE Evaluation Software
    3. 2 Quick Start
      1. 2.1 Default Jumper/Switch Configuration
      2. 2.2 ADS1x98ECG-FE Operation
    4. 3 Using the ADS1298ECG-FE Software
      1. 3.1 Application User Menu
      2. 3.2 Top-Level Application Controls
      3. 3.3 About Tab
      4. 3.4 ADC Register Tab
        1. 3.4.1 Standby and Reset Controls
        2. 3.4.2 Channel Registers Tab (ADC Register)
          1. 3.4.2.1 Global Channel Registers
          2. 3.4.2.2 Channel Control Registers
        3. 3.4.3 LOFF and RLD Tab (ADC Register)
          1. 3.4.3.1 Lead-Off Detection and Current Direction Control Registers
          2. 3.4.3.2 Right Leg Drive Derivation Control Registers
        4. 3.4.4 GPIO and OTHER Registers Tab (ADC Register)
          1. 3.4.4.1 Wilson Central and Augmented Lead Registers
        5. 3.4.5 Register Map (ADC Register)
      5. 3.5 Analysis Tab
        1. 3.5.1 Scope Tab (Anaysis)
          1. 3.5.1.1 Zoom Tool
        2. 3.5.2 Histogram Tab (Analysis)
        3. 3.5.3 FFT Tab
        4. 3.5.4 ECG Tab (Analysis)
      6. 3.6 Save Tab
    5. 4 ADS1x98ECG-FE Input Signals
      1. 4.1 Input Short Testing
      2. 4.2 Internal Test Signals Input
      3. 4.3 Temperature Sensor
      4. 4.4 Normal Electrode Input
        1. 4.4.1 Capturing 12-Lead ECG Signals
      5. 4.5 MVDD Input, RLD Measurement, RLD Positive Electrode Driver, and RLD Negative Electrode Driver
      6. 4.6 Lead Derivation
      7. 4.7 Wilson Center Terminal (WCT)
      8. 4.8 Right Leg Drive
        1. 4.8.1 RLD Common Mode Voltage
        2. 4.8.2 Driving the RLD Cable Shield
      9. 4.9 PACE Detection
    6. 5 ADS1298ECG-FE/ADS1198ECG-FE Hardware Details
      1. 5.1 Jumper Description
      2. 5.2 Power Supply
      3. 5.3 Clock
      4. 5.4 Reference
      5. 5.5 Analog Output Signals
      6. 5.6 Digital Signals
      7. 5.7 Analog Input Signals
        1. 5.7.1 Patient Simulator Input
        2. 5.7.2 Arbitrary Input Signals
  2. ASchematics, BOM, Layout, and ECG Cable Details
    1. A.1 Overview
    2. A.2 ADS1x98ECG-FE Front-End Board Schematics
    3. A.3 Bill of Materials
      1. Table 13. Bill of Materials: ADS1x98ECG-FE
    4. A.4 Printed Circuit Board Layout
    5. A.5 ECG Cable Details
  3. BExternal Optional Hardware
    1. B.1 Optional External Hardware (Not Included)
    2. B.2 ADS1x98ECG-FE Power-Supply Recommendations
  4. CSoftware Installation
    1. C.1 Minimum Requirements
    2. C.2 Installing the Software

2.1 Default Jumper/Switch Configuration

Figure 2 shows the jumpers found on the ADS1x98ECG-FE EVM and the respective factory default conditions for each.

c_Defaults2.pngFigure 2. ADS1x98ECG-FE Default Jumper Locations

Table 1 lists the jumpers and switches and the factory default conditions.

Table 1. ADS1x98ECG-FE Default Jumper/Switch Configuration

Jumper Default Position Description
JP1 Installed RLD feedback
JP2 Installed 1-2 AVDD selected for bipolar supply operation selected (AVDD = +2.5V)
JP3 Header Not Installed External Vref buffer not connected
JP4 Installed EVM +5V provided from J4 (power header)
JP5 Open PWDN pin controlled from J5 header (pulled up to DVDD)
JP6 to JP14 Header Not Installed (Pins 1-2 shorted on PCB) DC-coupled input signals
JP15 Installed 2-3 Shield drive is open
JP16 Installed Wilson Central Terminal (WCT) connected to INM for CH1 and CH4-8
JP17 Header Not Installed ECG shield drive
JP18 Installed 2-3 CLK connected to OSC1
JP19 Installed 1-2 OSC1 enabled
JP20 Installed 2-3 AVSS selected for bipolar supply operation (AVSS = -2.5V)
JP21 Installed 1-2 CS connected to DSP via J3.1
JP22 Installed 2-3 START comes from J3.14
JP23 Installed 1-2 CLKSEL set to 0 (ADS1198 uses Ext Master Clock (OSC1))
JP24 Installed 2-3 DVDD supply = 3.3V
JP25 Header Not Installed No external reference selected
JP26 Installed 1-2 (top) WCT connected to CH8- input
Installed 3-4 (bottom) ECG_V1 connected to CH8+ input
JP27 Installed 1-2 (top) WCT connected to CH7- input
Installed 3-4 (bottom) ECG_V5 connected to CH7+ input
JP28 Installed 1-2 (top) WCT connected to CH6- input
Installed 3-4 (bottom) ECG_V3 connected to CH5+ input
JP29 Installed 1-2 (top) WCT connected to CH5- input
Installed 3-4 (bottom) ECG_V4 connected to CH6+ input
JP30 Installed 1-2 (top) WCT connected to CH4- input
Installed 3-4 (bottom) ECG_V2 connected to CH4+ input
JP31 Installed 1-2 (top) ECG_RA connected to CH3- input
Installed 3-4 (bottom) ECG_LL connected to CH3+ input
JP32 Installed 1-2 (top) ECG_RA connected to CH2- input
Installed 3-4 (bottom) ECG_ LA connected to CH2+ input
JP33 Installed 1-2 (top) WCT connected to CH1- input
Installed 3-4 (bottom) ECG_V6 connected to CH1+ input