SBAK020 April   2025 ADC3683-SEP

PRODUCTION DATA  

  1.   1
  2.   Single-Event Effects Test Report of the ADC3683-SEP dual 18-bit 65-MSPS ADC
  3.   Trademarks
  4. Introduction
  5. Single-Event Effects
  6. Irradiation Facility and Setup
  7. Depth, Range, and LETEFF Calculations
  8. Test Setup and Procedures
  9. Destructive Single-Event Effects (DSEE)
  10. Single-Event Transients (SET)
  11. Event Rate Calculations
  12. Summary
  13. 10References

Test Setup and Procedures

SEE testing was performed on an ADC3683-SEP device solder down on an ADC3683-SEP EVM. For the SEL, the device was powered up to a voltage of 1.9V at approximately 125°C. For the SET characterization, the ADC3683-SEP was tested at room temperature at approximately 25°C operating under nominal conditions for power supplies. Two power supplies were used to power AVDD and IOVDD, each using 1.8V.

For SEU events, the DCLK output signal was monitored, with DCLK being the clock signal supplied to the FPGA. When the DCLK signal experiences an upset, the data on the data lines is not valid. As DCLK by default is always toggling and outputting a constant and continuous signal, when there is a significant deviation from normal, an event has occurred. To monitor DCLK events, a National Instruments™ (NI) PXIe-5172 scope card connected to USER_LED3 on the TSW1400EVM was used, which goes high when a valid clock from the ADC is not received, which is defined as an event occurring.

The scope was configured to capture events using a rising edge trigger. AVDD and IOVDD currents were also monitored during SEU testing. However, the currents were not used in determining whether an event has occurred. Events were observed and are characterized in Table 5-1. See Section 7 for more details.

All equipment was controlled and monitored using a custom-developed LabVIEW™ program (PXI-RadTest) running on a HP-Z4® desktop computer. The computer communicates with the PXI chassis through an MXIExpress cable and a NI PXIe-8381 remote control module. Figure 5-1 shows a block diagram of the setup used for SEE testing of the ADC3683-SEP. Table 5-1 lists the connections, limits, and compliance values used during the testing. During the SEL testing, the device was heated to 125°C by using a Closed-Loop PID controlled heat gun (MISTRAL 6 System 120V, 2400W). For SEU testing, the device was tested at room temperature. No cooling or heating was applied to the DUT. Die temperature was verified using a FLIR IR-camera prior to the SEE test campaign.

Table 5-1 Equipment Set and Parameters Used for SEE Testing the ADC3683-SEP
Name Equipment Used Value Set
AVDD KeySight E36311 1.9V
IOVDD KeySight E36311 1.9V
EVM Board Supply KeySight E36311 1.8V
DCLKIN R&S SML01 Sig Gen 292.5MHz
Channel A R&S SGS100A 20MHz
CLK R&S SGS100A 65MHz

All boards used for SEE testing were fully checked for functionality. Dry runs were also performed to make sure that the test system was stable under all bias and load conditions prior to being taken to the TAMU facility. During the heavy-ion testing, the LabVIEW control program powered up the ADC3683-SEP device and set the external sourcing and monitoring functions of the external equipment. After functionality and stability had been confirmed, the beam shutter was opened to expose the device to the heavy-ion beam. The shutter remained open until the target fluence was achieved (determined by external detectors and counters). During irradiation, the NI scope cards continuously monitored the signals. When the DCLK voltage changes from low to high (using a positive edge trigger), a data capture was initiated. In addition to monitoring the DCLK signal, AVDD and IOVDD current were monitored at all times.

ADC3683-SEP Block Diagram of SEE Test
                    Setup With the ADC3683-SEP Figure 5-1 Block Diagram of SEE Test Setup With the ADC3683-SEP