SBAK020 April   2025 ADC3683-SEP

PRODUCTION DATA  

  1.   1
  2.   Single-Event Effects Test Report of the ADC3683-SEP dual 18-bit 65-MSPS ADC
  3.   Trademarks
  4. 1 Introduction
  5. 2 Single-Event Effects
  6. 3 Irradiation Facility and Setup
  7. 4 Depth, Range, and LETEFF Calculations
  8. 5 Test Setup and Procedures
  9. 6 Destructive Single-Event Effects (DSEE)
  10. 7 Single-Event Transients (SET)
  11. 8 Event Rate Calculations
  12. 9 Summary
  13. 10References

4 Depth, Range, and LETEFF Calculations

The ADC3683-SEP is fabricated in the TI CMOS C021(C021, 65-nm process with a Back-End-Of-Line (BEOL) stack consisting of eight layers of standard thickness aluminum metal. The total stack height from the surface of the passivation to the silicon surface is 20.7μm based on nominal layer thickness. Accounting for energy loss through the 1mil thick Aramica beam port window, the 40mm air gap and the BEOL stack over the ADC3683-SEP, the effective LET (LETEFF) at the surface of the silicon substrate, the depth, and the ion range was determined with the SEUSS 2020 Software [4] (provided by the Texas A&M Cyclotron Institute and based on the latest SRIM-2013 models). Table 4-1 lists the results.
Table 4-1 Ion LET EFF Depth and Range in Silicon
Ion Type Angle of Incidence (°) RangeEFF in Silicon (µm) LETEFF (MeV × cm2/ mg)
109Ag 0 76.6 51.12