ZHCSLD2E may 2020 – july 2023 UCC28782
PRODUCTION DATA
The UCC28782 is intended to control active-clamp flyback (ACF) converters in high-efficiency off-line applications, and is optimized to be used with universal AC input, from 85 VAC to 265 VAC, at 47 Hz to 63 Hz. An external depletion-mode MOSFET connected between the switch node of the converter and the SWS / P13 pins of this controller is required to charge the VDD capacitor during start-up, and to perform ZVS sensing during normal operation.
Once the VVDD reaches the UVLO turn-on threshold at 17 V (typical), the VDD rail should be kept within the bias supply operating voltage range listed in the Recommended Operating Conditions table in Section 7.3. To avoid the possibility that the device might stop switching, VVDD should not be allowed to fall below the maximum UVLO turn-off threshold at 11.17 V.
Under the condition of LPM operation, the clamp capacitor CCLAMP is charged higher than the reflected voltage by the primary leakage inductance energy. On transition from LPM to ABM, this over-charge of CCLAMP is delivered to the output during the first event where PWMH is high. The peak current is determined by the impedance formed by the resonance of the leakage inductance with the clamp capacitance, and it may be quite high. On the secondary side, the primary current is multiplied by the transformer turns-ratio. Verify that the pulse-current ratings of the high-side MOSFET and the output rectifier are adequate for these peak currents.
During power-stage switching, high dv/dt may appear to induce positive or negative noise on various pins of the UCC28782 that apparently exceeds their respective Absolute Maximum ratings. This kind of noise is often less than 10~20 ns in duration. If such measurements are made, ensure that "tip & barrel" probing techniques are used to eliminate ground-bounce and noise pickup on oscilloscope probe grounding wires. Make sure that the probe's GND reference is an AGND node as close to the IC as possible. If excess voltage is still measured, verify that the maximum source or sink current of the pin is not exceeded.
Under certain special circumstances, such as a brief short-circuit or an extended overshoot on the converter output, switching slows or stops until the condition clears and the clamp capacitor CCLAMP may be overdischarged by a low RBLEED value. A low VCLAMP reflects to the Auxiliary winding and may cause VS to go low before PWMH goes low. If this happens the UCC28782 will stop switching and VDD will fall to the UVLO threshold and cycle through a restart. If this situation occurs, it may be mitigated by one or more of the following steps:
Use an edge-triggered (not level-triggered) isolator/driver with short power-up delay for the high-side switch on the primary side.
Ensure the value of RBLEED is not too low.
Reduce the value of the RDM resistor judiciously.
In cases where there is no DCM ringing after PWMH goes low, try adding a positive offset voltage to VS to raise the apparent ZCD threshold.
The rectifier on the output winding may be a P-N diode, a Schottky diode, or a synchronous-rectifier (SR) MOSFET for higher efficiency. The current rating of this rectifier should be appropriate for the resonant flyback current and its peak current rating should accomodate the CCLAMP charge balancing peak current. Besides the output voltage plus reflected bulk voltage impressed across the rectifier during PWML on-time, consideration for additional voltage spikes from various transient conditions should be made. Sources of voltage spikes on the rectifier include: hard switching of the low-side MOSFET on the primary, non-ZCS turn-off of the high-side MOSFET on the primary, and non-ZCS turn-off of an SR-MOSFET.
Regardless of cause of each of these spike sources, it is important to ensure that the peak voltage across the rectifier does not exceed its maximum rating. This may be accomplished in several ways, by implementing one or more of the alternative methods listed here:
Choose a rectifier with a higher voltage rating.
Add a TVS-type voltage-clamping device across the rectifier.
Add or improve an R-C snubber across the rectifier.
Slow down falling dv/dt of the low-side switch on the primary side.
Minimize leakage inductance of the transformer secondary winding.
Use an edge-triggered (not level-triggered) isolator/driver with short power-up delay for the high-side switch on the primary side.
Minimize the stray inductance in the VDS-sense path of the SR controller.
In case of reverse current conduction, choose an SR controller with shorter minimum on-time.
Add or increase the value of a resistor in series with the gate of the SR-MOSFET, to slow down its di/dt during non-ZCS turn-off.
Reduce the value of the RDM resistor judiciously, to reduce the maximum negative peak primary current by reducing maximum PWMH on-time.