The UP and DOWN pins are the inputs that initiate a sequence up or down. Both pins incorporate an accurate comparator with a threshold voltage of V_{TH_UP} = 599mV (for UP) and V_{TH_DOWN} = 498mV (for DOWN) with an accuracy of ±3% for both inputs.

A fixed hysteresis of 100mV is incorporated in both comparators for noise stability. The edges on these pins are used to initiate the command as:

• Rising edge on UP starts a sequence up.
• Falling edge on DOWN starts a sequence down.

The UP voltage is also used in the state machine as a latch method to prevent oscillations during a FAULT. In order to move away from the Fault state, the UP voltage has to be logic low. As UP is a comparator with 100mV of hysteresis, depending on whether the V_UP have been previously above the V_{TH_UP}, the logic low level is:

• V_{TH_UP} ≤ 599mV (typ) if UP has not previously been above V_{TH_UP}.
• V_{UP_TH} (typically 600mV) – 100mV ≤ 500mV (typ) if UP has previously crossed V_{UP_TH}.

These inputs can be driven externally by a house-keeping controller or via a resistive divider connected to a voltage source.

As these inputs are edge sensitive, is important to have a stable input voltage (UVLO_RISE < V_IN < 14V) for at least 2.8ms (t_{Start_up_delay}) before sending the sequence up command. This is due to internal time constants in the device. During sequence down, it's important to maintain a stable input voltage until the SEQ_DONE flag is set low to allow all rails to be properly sequenced down.

As both the UP and DOWN pins have accurate undervoltage comparators, the user can program the voltage at which the system will automatically start the sequence up and down when monitoring a main power rail (V_MAIN) via a resistive divider. However, in this case it is important to make sure the rising and falling edge are sent when V_IN is stable, as mentioned before. A capacitor can be added from UP to GND to delay the signal when the slew rate at V_MAIN is fast.

Usually the designer knows the voltages at which it's desired to start the sequence up (referred to as V_{UP_IDEAL}) and down (referred to as V_{DOWN_IDEAL}). With that information we can calculate the resistive divider values using Equation 17 and Equation 18. Usually the top resistor is fixed to a 10kΩ value.

where:

• V_{TH_UP}= 598mV (typical)
• V_{TH_DOWN}= 498mV (typical)

Once the designer knows the actual (real) resistive divider values, Equation 19 and Equation 20 can be used to calculate the sequence up and down nominal voltages as:

If desired, to select the capacitance (C_DELAY) for the UP pin we can use Equation 21.

where:

• t_DELAY (s) is the desired delay time in seconds (at least 2.8ms after V_IN > UVLO_RISE).
• R_TH is the Thévenin equivalent resistance. In this case the parallel between R_TOP and R_BOTTOM in ohms.
  • Equation 22. ${\mathrm{R}}_{\mathrm{T}\mathrm{H}} \left(\mathrm{\Omega }\right)=\frac{{\mathrm{R}}_{\mathrm{T}\mathrm{O}\mathrm{P}\mathrm{ }}\left(\mathrm{\Omega }\right)\times {\mathrm{R}}_{\mathrm{B}\mathrm{O}\mathrm{T}\mathrm{T}\mathrm{O}\mathrm{M}}\left(\mathrm{\Omega }\right)}{{\mathrm{R}}_{\mathrm{T}\mathrm{O}\mathrm{P}\mathrm{ }}\left(\mathrm{\Omega }\right)+{\mathrm{R}}_{\mathrm{B}\mathrm{O}\mathrm{T}\mathrm{T}\mathrm{O}\mathrm{M}}\left(\mathrm{\Omega }\right)}$
• V_TH is the Thévenin equivalent voltage. In this case the voltage at V_UP during steady state operation in volts.
  • Equation 23. ${\mathrm{V}}_{\mathrm{T}\mathrm{H}} \left(\mathrm{V}\right)=\left(\frac{{\mathrm{R}}_{\mathrm{B}\mathrm{O}\mathrm{T}\mathrm{T}\mathrm{O}\mathrm{M}}\left(\mathrm{\Omega }\right)}{{\mathrm{R}}_{\mathrm{T}\mathrm{O}\mathrm{P}\mathrm{ }}\left(\mathrm{\Omega }\right)+{\mathrm{R}}_{\mathrm{B}\mathrm{O}\mathrm{T}\mathrm{T}\mathrm{O}\mathrm{M}}\left(\mathrm{\Omega }\right)}\right)\times \mathrm{ }{\mathrm{V}}_{\mathrm{M}\mathrm{A}\mathrm{I}\mathrm{N}}\left(V\right)$
• V(t) is the voltage at UP (V_UP) which will start the sequence up. In this case 598mV ±3%, in volts.

Figure 7-11 Monitor a Main Rail to Automatically Start the Sequence UP and DOWN