10.1 Layout Guidelines

An optimal layout can greatly improve transient performance, PSRR, and noise. To minimize the voltage droop on the input of the device during load transients, connect the capacitance on IN and BIAS as close as possible to the device. This capacitance also minimizes the effects of parasitic inductance and resistance of the input source and can therefore improve stability. To achieve optimal transient performance and accuracy, connect the top side of R₁ in Figure 27 as close as possible to the load. If BIAS is connected to IN, TI recommends connecting BIAS as close to the sense point of the input supply as possible. This connection minimizes the voltage droop on BIAS during transient conditions and can improve the turnon response.

10.2 Layout Example

Figure 32. Layout Schematic (VQFN Packages)

10.3 Thermal Protection

Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is enabled. Depending on power dissipation, thermal resistance, and ambient temperature the thermal protection circuit may cycle ON and OFF. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating.

Activation of the thermal protection circuit indicates excessive power dissipation or inadequate heatsinking. For reliable operation, limit junction temperature to 125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection must trigger at least 40°C above the maximum expected ambient condition of the application. This condition produces a worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load.

The internal protection circuitry of the TPS742 devices is designed to protect against overload conditions. This circuitry is not intended to replace proper heatsinking. Continuously running the TPS742 devices into thermal shutdown degrades device reliability.

10.4 Thermal Considerations

Using the thermal metrics Ψ_JT and Ψ_JB, shown in Thermal Information, the junction temperature can be estimated with corresponding formulas (given in Equation 6). For backwards compatibility, an older θ_JC,Top parameter is listed as well.

Equation 6.

where

• P_D is the power dissipation given by P_D = (V_IN – V_OUT) × I_OUT
• T_T is the temperature at the center-top of the IC package
• T_B is the PCB temperature measured 1mm away from the IC package on the PCB surface (as Figure 33 shows).

For more information about measuring T_T and T_B, see the application note Using New Thermal Metrics (SBVA025), available for download at www.ti.com.

1. T_T is measured at the center of both the X- and Y-dimensional axes.

2. T_B is measured below the package lead on the PCB surface.

Figure 33. Measuring Points for T_T and T_B

Compared with θ_JA, the new thermal metrics Ψ_JT and Ψ_JB are less independent of board size, but they do have a small dependency. Figure 34 shows characteristic performance of Ψ_JT and Ψ_JB versus board size.

Looking at Figure 34, the RGW package thermal performance has negligible dependency on board size. The KTW package, however, does have a measurable dependency on board size. This dependency exists because the package shape is not point‐symmetric to an IC center. In the KTW package, for example (see Figure 33), silicon is not beneath the measuring point of T_T, which is the center of the X and Y dimension, so that Ψ_JT has a dependency. Also, because of that non-point‐symmetry, device heat distribution on the PCB is not point‐symmetric, either, so that Ψ_JB has a dependency.

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Figure 34. Ψ_JT and Ψ_JB vs Board Size

For a more detailed discussion of why TI does not recommend using θ_JC,Top to determine thermal characteristics, refer to the application note Using New Thermal Metrics (SBVA025), available for download at www.ti.com. Also, refer to the application note IC Package Thermal Metrics (SPRA953) (also available on the TI website) for further information.