JAJSP34 データシート

ZHCS614G October 2011 – September 2022 TPS40422

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

RSB|40
- MPQF185C
RHA|40
- MPQF135D

散热焊盘机械数据 (封装 | 引脚)

订购信息

7.5 Electrical Characteristics

T_J = –40°C to 125°C, V_IN = V_DD = 12 V, f_SW = 500 kHz, all parameters at zero power dissipation (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
INPUT SUPPLY
V_VDD	Input supply voltage range		4.5		20	V
I_VDD	Input operating current	Switching, no driver load		18	25	mA
I_VDD	Input operating current	Not switching		15	20	mA
UVLO
V_IN(on)	Input turn on voltage⁽²⁾	Default settings		4.25		V
V_IN(off)	Input turn off voltage⁽²⁾	Default settings		4		V
V_INON(rng)	Programmable range for turn on voltage		4.25		16	V
V_INOFF(rng)	Programmable range for turn off voltage		4		15.75	V
V_IN_ONOFF(acc)	Turn on and turn off voltage accuracy⁽¹⁾	4.5 V ≤ V_VDD ≤ 20 V, all VIN_ON and VIN_OFF settings	–5%		5%
ERROR AMPLIFIER
V_FB	Feedback pin voltage	0°C ≤ T_J ≤ 85°C	597	600	603	mV
V_FB	Feedback pin voltage	–40°C ≤ T_J ≤ 125°C	594	600	606	mV
A_OL	Open-loop gain⁽¹⁾		80			dB
G_BWP	Gain bandwidth product⁽¹⁾			24		MHz
I_FB	FB pin bias current (out of pin)	V_FB = 0.6 V			50	nA
I_COMP	Sourcing	V_FB = 0 V	1	3		mA
I_COMP	Sinking	V_FB = 1 V	3	9		mA
BP6 REGULATOR
V_BP6	Output voltage	I_BP6 = 10 mA	6.2	6.5	6.8	V
V_BP6	Dropout voltage	V_VIN – V_BP6, V_VDD = 4.5 V, I_BP6 = 25 mA		70	120	mV
I_BP6	Output current	V_VDD = 12 V	120			mA
V_BP6UV	Regulator UVLO voltage⁽¹⁾		3.3	3.55	3.8	V
V_BP6UV(hyst)	Regulator UVLO voltage hysteresis⁽¹⁾		230	255	270	mV
BPEXT
V_{BPEXT(swover)}	BPEXT switch-over voltage		4.5	4.6		V
V_hys(swover)	BPEXT switch-over hysteresis		100		200	mV
V_BPEXT(do)	BPEXT dropout voltage	V_BPEXT–V_BP6, V_BPEXT = 4.8 V, I_BP6 = 25 mA			100	mV
BOOTSTRAP
V_BOOT(drop)	Bootstrap voltage drop	I_BOOT = 5 mA		0.7	1.0	V
BP3 REGULATOR
V_BP3	Output voltage	V_VDD = 4.5 V, I_BP3 ≤ 5 mA	3.1	3.3	3.5	V
OSCILLATOR
f_SW	Adjustment range		100		1000	kHz
f_SW	Switching frequency	R_RT = 40 kΩ	450	500	550	kHz
V_RMP	Ramp peak-to-peak⁽¹⁾			V_VDD/8.2		V
V_VLY	Valley voltage⁽¹⁾		0.7	0.8	1.0	V
SYNCHRONIZATION
V_SYNCH	SYNC high-level threshold		2.0			V
V_SYNCL	SYNC low level threshold				0.8	V
t_SYNC	Minimum SYNC pulse width				100	ns
f_SYNC(max)	Maximum SYNC frequency⁽⁴⁾		2000			kHz
f_SYNC(min)	Minimum SYNC frequency⁽⁴⁾				200
	SYNC frequency range (increase from nominal oscillator frequency)		–20%		20%
PWM
t_OFF(min)	Minimum off time		90	100		ns
t_ON(min)	Minimum on pulse⁽¹⁾			90	130	ns
t_DEAD	Output driver dead time	HDRV off to LDRV on	15	30	45	ns
t_DEAD	Output driver dead time	LDRV off to HDRV on	15	30	45	ns
SOFT START
t_SS	Soft-start time	Factory default settings	2.4	2.7	3.0	ms
t_SS	Accuracy over range⁽¹⁾	600 µs ≤ t_SS ≤ 9 ms	–15%		15%
t_ON(delay)	Turn-on delay time⁽³⁾	Factory default settings		0		ms
t_OFF(delay)	Turn-off delay time	Factory default settings		0		ms
REMOTE SENSE AMPLIFIER
V_DIFFO(err)	Error voltage from DIFFO1 to (V_SNS1– G_SNS1)	(V_SNS1– G_SNS1) = 0.6 V	–5		5	mV
		(V_SNS1– G_SNS1) = 1.2 V	–8		8
		(V_SNS1– G_SNS1) = 3.0 V	–17		17
BW	Closed-loop bandwidth⁽¹⁾		2			MHz
V_DIFFO(max)	Maximum DIFFOx output voltage		V_BP6-0.2			V
I_DIFFO	Sourcing		1			mA
I_DIFFO	Sinking		1			mA
DRIVERS
R_HS(up)	High-side driver pull-up resistance	(V_BOOT–V_SW) = 6.5 V, I_HS = -40 mA	0.8	1.5	2.5	Ω
R_HS(dn)	High-side driver pull-down resistance	(V_BOOT–V_SW) = 6.5 V, I_HS = 40 mA	0.5	1.0	1.5
R_LS(up)	Low-side driver pull-up resistance	I_LS = -40 mA	0.8	1.5	2.5
R_LS(dn)	Low-side driver pull-down resistance	I_LS = 40 mA	0.35	0.70	1.40
t_HS(rise)	High-side driver rise time ⁽¹⁾	C_LOAD = 5 nF		15		ns
t_HS(fall)	High-side driver fall time ⁽¹⁾	C_LOAD = 5 nF		12
t_LS(rise)	Low-side driver rise time ⁽¹⁾	C_LOAD = 5 nF		15
t_LS(fall)	Low-side driver fall time ⁽¹⁾	C_LOAD = 5 nF		10
CURRENT SENSING AMPLIFIER
V_CS(rng₎	Differential input voltage range	V_CSxP-V_CSxN	-60		60	mV
V_CS(cmr)	Input common-mode range		0		V_BP6–0.2	V
V_CS(os)	Input offset voltage	V_CSxP = V_CSxN = 0 V	-3		3	mV
A_CS	Current sensing gain			15.00		V/V
V_CS(out)	Amplfier output	(V_CSxP-V_CSxN) = 20 mV	270	300	330	mV
f_C0	Closed-loop bandwidth⁽¹⁾		3	5		MHz
V_CS(chch)	Amplifier output difference between CH1, CH2	(V_CS1P– V_CS1N) = (V_CS2P–V_CS2N) = 20 mV, T_J = 25°C	-5.00%		5.00%
V_CS(chch)	Amplifier output difference between CH1, CH2	(V_CS1P– V_CS1N) = (V_CS2P–V_CS2N) = 20 mV, T_J = 85°C	-6.67%		6.67%
CURRENT LIMIT
t_OFF(oc)	Off-time between restart attempts	Hiccup mode		7×t_SS		ms
DCR	Inductor DCR current sensing calibration value	Factory default settings		0.488		mΩ
DCR	Inductor DCR current sensing calibration value	Programmable range	0.240		15.500	mΩ
I_OC(flt)	Output current overcurrent fault threshold	Factory default settings		30		A
I_OC(flt)	Output current overcurrent fault threshold	Programmable range	3		50	A
I_OC(warn)	Output current overcurrent warning threshold	Factory default settings		27		A
I_OC(warn)	Output current overcurrent warning threshold	Programmable range	2		49	A
I_OC(tc)	Output current fault/warning temperature coefficient⁽¹⁾		3900	4000	4100	ppm/°C
I_OC(acc)	Output warning and fault accuracy	(V_CSxP-V_CSxN) = 30 mV	–15%		15%
PGOOD
V_FBPGH	FB PGOOD high threshold	Factory default settings		675		mV
V_FBPGL	FB PGOOD low threshold	Factory default settings		525		mV
V_PG(acc)	PGOOD accuracy over range	4.5 V ≤ V_VDD ≤ 20 V, 468 mV ≤ V_PGOOD ≤ 675 mV	–4%		4%
V_pg(hyst)	FB PGOOD hysteresis voltage			25	40	mV
R_PGOOD	PGOOD pulldown resistance	V_FB = 0, I_PGOOD = 5 mA		40	70	Ω
I_PGOOD(lk)	PGOOD pin leakage current	No fault, V_PGOOD = 5 V			20	µA
OUTPUT OVERVOLTAGE/UNDERVOLTAGE
V_FBOV	FB pin over voltage threshold	Factory default settings		700		mV
V_FBUV	FB pin under voltage threshold	Factory default settings		500		mV
V_UVOV(acc)	FB UV/OV accuracy over range	4.5 V ≤ V_VDD ≤ 20 V	–4%		4%
OUTPUT VOLTAGE TRIMMING AND MARGINING
V_FBTM(step)	Resolution of FB steps with trim and margin			2		mV
t_FBTM(step)	Transition time per trim or margin step	After soft-start time		30		µs
V_FBTM(max)	Maximum FB voltage with trim and/or margin			660		mV
V_FBTM(min)	Minimum FB voltage with trim or margin only			480		mV
V_FBTM(min)	Minimum FB voltage range with trim and margin combined			420		mV
V_FBMH	Margin high FB pin voltage	Factory default settings		660		mV
V_FBML	Margin low FB pin voltage	Factory default settings		540		mV
TEMPERATURE SENSE AND THERMAL SHUTDOWN
T_SD	Junction thermal shutdown temperature⁽¹⁾		135	145	155	°C
T_HYST	Thermal shutdown hysteresis⁽¹⁾		15	20	25	°C
I_TSNS(ratio)	Ratio of bias current flowing out of TSNS pin, state 2 to state 1		9.7	10.0	10.3
I_TSNS	State 1 current out of TSNSx pin⁽¹⁾			10		µA
I_TSNS	State 2 current out of TSNSx pin⁽¹⁾			100		µA
V_TSNS	Voltage range on TSNSx pin⁽¹⁾		0		1.00	V
T_SNS(acc)	External temperature sense accuracy⁽¹⁾	0°C ≤ T_J ≤ 125°C	–5		5	°C
T_OT(flt)	Overtemperature fault limit⁽¹⁾	Factory default settings		145		°C
	OT fault limit range⁽¹⁾		120		165	°C
T_OT(warn)	Overtemperature warning limit⁽¹⁾	Factory default settings		125		°C
	OT warning limit range⁽¹⁾		100		140	°C
T_OT(step)	OT fault/warning step			5		°C
T_OT(hys)	OT fault/warning hysteresis⁽¹⁾		15	20	25	°C
MEASUREMENT SYSTEM
M_VOUT(rng)	Output voltage measurement range⁽¹⁾		0.5		5.8	V
M_VOUT(acc)	Output voltage measurement accuracy	V_OUT = 1.0 V	–2.0%		2.0%
M_IOUT(rng)	Output current measurement signal range⁽¹⁾	V_CSxP–V_CSxN, 0.2440 mΩ ≤ IOUT_CAL_GAIN ≤ 0.5795 mΩ	0		24	mV
		V_CSxP–V_CSxN, 0.5796 mΩ ≤ IOUT_CAL_GAIN ≤ 1.1285 mΩ	0		40
		V_CSxP–V_CSxN, 1.1286 mΩ ≤ IOUT_CAL_GAIN ≤ 15.5 mΩ	0		60
M_IOUT(acc)	Output current measurement accuracy	I_OUT ≥ 20 A, DCR = 0.5 mΩ	–1.0		1.0	A
PMBus ADDRESSING
I_ADD	Address pin bias current		9.24	10.50	11.76	µA
PMBus INTERFACE
V_IH	Input high voltage, CLK, DATA, CNTLx		2.1			V
V_IL	Input low voltage, CLK, DATA, CNTLx				0.8	V
I_IH	Input high level current, CLK, DATA		–10		10	µA
I_IL	Input low level current, CLK, DATA		–10		10	mA
I_CTNL	CNTL pin pull-up current			6		µA
V_OL	Low-level output voltage, DATA, ⁽¹⁾	4.5 V ≤ V_VDD ≤ 20 V, I_OUT = 4 mA			0.4	V
I_OH	High-level output open-drain leakage current, DATA, SMBALRT	V_OUT = 5.5 V	0		10	µA
C_OUT	Output capacitance, CLK, DATA⁽¹⁾				1	pF
F_PMB	PMBus operating frequency range⁽¹⁾	Slave mode	10		400	kHz
t_BUF	Bus free time between START and STOP⁽¹⁾		1.3			µs
t_HD:STA	Hold time after repeated START⁽¹⁾		0.6			µs
t_SU:STA	Repeated START setup time⁽¹⁾		0.6			µs
t_SU:STO	STOP setup time⁽¹⁾		0.6			µs
t_HD:DAT	Data hold time⁽¹⁾	Receive mode	0			ns
t_HD:DAT	Data hold time⁽¹⁾	Transmit mode	300			ns
t_SU:DAT	Data setup time⁽¹⁾		100			ns
t_TIMEOUT	Error signal/detect⁽¹⁾		25		35	ms
t_LOW:MEXT	Cumulative clock low master extend time⁽¹⁾				10	ms
t_LOW:SEXT	Cumulative clock low slave extend time⁽¹⁾				25	µs
t_LOW	Clock low time⁽¹⁾		1.3			µs
t_HIGH	Clock high time⁽¹⁾		0.6			µs
t_FALL	CLK/DATA fall time⁽¹⁾				300	ns
t_RISE	CLK/DATA rise time⁽¹⁾				300	ns

(1) Specified by design. Not production tested.

(2) Hysteresis of at least 150 mV is specified by design.

(3) The minimum turn-on delay is 50 µs, when TON_DELAY is set to a factor of zero.

(4) When using SYNC, the switching frequency is set to one-half the SYNC frequency.