5.9 Power Supply Sequences

This section describes the power-up and power-down sequence required to ensure proper device operation. The power supply names described in this section comprise a superset of a family of compatible devices. Some members of this family will not include a subset of these power supplies and their associated device modules. Refer to the Section 4.2, Ball Characteristics of the Section 4, Terminal Configuration and Functions to determine which power supplies are applicable.

Figure 5-2 and Figure 5-3 describe the device Power Sequencing when RTC-mode is used.

Figure 5-2 Power-Up Sequencing

1. Grey shaded areas are windows where it is valid to ramp the voltage rail.
2. Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
3. If RTC-mode is used then vdda_rtc, vdd_rtc and vddshv5 must be individually powered with separate power supplies and cannot be combined with other rails.
4. vdd must ramp before or at the same time as vdd_mpu, vdd_gpu, vdd_dsp and vdd_iva.
5. vdd_mpu, vdd_gpu, vdd_dsp, vdd_iva can be ramped at the same time or can be staggered.
6. If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.
7. vddshv8 is separated out to show support for dual voltage. If single voltage is used then vddshv8 can be combined with other vddshvn rails but vddshv8 must ramp after vdd.
8. vdds and vdda rails must not be combined together.
9. Pulse duration: rtc_porz must remain low 1ms after vdda_rtc, vddshv5, and vdd_rtc are ramped and stable.
10. The SYS_32K source must be stable and at a valid frequency 1ms prior to de-asserting rtc_porz high.
11. Pulse duration: porz must remain low a minimum of 12P⁽¹⁵⁾ after xi_osc0 is stable and at a valid frequency. porz must also remain low until all supply rails are valid and stable. resetn must be high prior to, or simultaneous with, porz rising. During initial power-up, resetn can rise any time after, or concurrently with, its supply voltage, vddshv3 rising.
12. Setup time: sysboot[15:0] pins must be valid 2P⁽¹⁵⁾ before porz is de-asserted high.
13. Hold time: sysboot[15:0] pins must be valid 15P⁽¹⁵⁾ after porz is de-asserted high.
14. porz to rstoutn delay is 2ms.
15. P = 1/(SYS_CLK1/610) frequency in ns.

Figure 5-3 Power-Down Sequencing

1. xi_osc0 can be turned off anytime after porz assertion and must be turned off before vdda_osc voltage rail is shutdown.
2. Grey shaded areas are windows where it is valid to ramp the voltage rail.
3. Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
4. If RTC-mode is supported then vdda_rtc, vdd_rtc and vddshv5 must be individually powered with separate power supplies and cannot be combined with other rails.
5. vdd_mpu, vdd_gpu, vdd_dsp, vdd_iva can be ramped at the same time or can be staggered.
6. vdd must ramp after or at the same time as vdd_mpu, vdd_gpu, vdd_dsp and vdd_iva.
7. If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v. vddshv[1-7,9-11] is allowed to ramp down at either of the two points shown in the timing diagram in either 1.8V mode or in 3.3V mode. If vddshv[1-7,9-11] ramps down at the later time in the diagram then the board design must guarantee that the vddshv[1-7,9-11] rail is never higher than 2.0 V above the vdds18v rail.
8. vddshv8 is separated out to show support for dual voltage. If a dedicated LDO/supply source is used for vddshv8, then vddshv8 ramp down should occur at one of the two earliest points in the timing diagram. If vddshv8 is powered by the same supply source as the other vddshvn rails, then it is allowed to ramp down at either of the last two points in the timing diagram.

Figure 5-4 describes the RTC-mode Power Sequencing.

Figure 5-4 RTC Mode Sequencing

1. Grey shaded areas are windows where it is valid to ramp the voltage rail.
2. Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
3. vdd must ramp down after or at the same time as vdd_mpu, vdd_gpu, vdd_dsp and vdd_iva.
4. vdd_mpu, vdd_gpu, vdd_dsp, vdd_iva can be ramped at the same time or can be staggered.
5. vdd must ramp up before or at the same time as vdd_mpu, vdd_gpu, vdd_dsp and vdd_iva.
6. If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.
7. vddshv8 is separated out to show support for dual voltage. If single voltage is used then vddshv8 can be combined with other vddshvn rails but vddshv8 must ramp down before vdd and must ramp up after vdd.
8. If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v. vddshv[1-7,9-11] is allowed to ramp down at either of the two points shown in the timing diagram in either 1.8V mode or in 3.3V mode. If vddshv[1-7,9-11] ramps down at the later time in the diagram then the board design must guarantee that the vddshvn rail is never higher than 2.0 V above the vdds18v rail.
9. vddshv8 is separated out to show support for dual voltage. If a dedicated LDO/supply source is used for vddshv8, then vddshv8 ramp down should occur at one of the two earliest points in the timing diagram. If vddshv8 is powered by the same supply source as the other vddshvn rails, then it is allowed to ramp down at either of the last two points in the timing diagram.

Figure 5-5 and Figure 5-6 describe the device Power Sequencing when RTC-mode is NOT used.

Figure 5-5 Power-Up Sequencing

1. Grey shaded areas are windows where it is valid to ramp the voltage rail.
2. Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
3. If RTC-mode is not supported then the following combinations are approved:
   - vdda_rtc can be combined with vdds18v
   - vdd_rtc can be combined with vdd
   - vddshv5 can be combined with other 1.8V or 3.3V vddshvn rails.
   If combinations listed above are not followed then sequencing for these 3 voltage rails should follow the RTC mode timing requirements.
4. vdd must ramp before or at the same time as vdd_mpu, vdd_gpu, vdd_dsp and vdd_iva.
5. vdd_mpu, vdd_gpu, vdd_dsp, vdd_iva can be ramped at the same time or can be staggered.
6. If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.
7. vddshv8 is separated out to show support for dual voltage. If single voltage is used then vddshv8 can be combined with other vddshvn rails but vddshv8 must ramp after vdd.
8. vdds and vdda rails must not be combined together, with the one exception of vdda_rtc when RTC-mode is not supported.
9. Pulse duration: rtc_porz must remain low 1ms after vdda_rtc, vddshv5, and vdd_rtc are ramped and stable.
10. The SYS_32K source must be stable and at a valid frequency 1ms prior to de-asserting rtc_porz high.
11. Pulse duration: porz must remain low a minimum of 12P⁽¹⁵⁾ after xi_osc0 is stable and at a valid frequency. porz must also remain low until all supply rails are valid and stable. resetn must be high prior to, or simultaneous with, porz rising. During initial power-up, resetn can rise any time after, or concurrently with, its supply voltage, vddshv3 rising.
12. Setup time: sysboot[15:0] pins must be valid 2P⁽¹⁵⁾ before porz is de-asserted high.
13. Hold time: sysboot[15:0] pins must be valid 15P⁽¹⁵⁾ after porz is de-asserted high.
14. porz to rstoutn delay is 2ms.
15. P = 1/(SYS_CLK1/610) frequency in ns.

Figure 5-6 Power-Down Sequencing

1. Grey shaded areas are windows where it is valid to ramp the voltage rail.
2. Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
3. xi_osc0 can be turned off anytime after porz assertion and must be turned off before vdda_osc voltage rail is shutdown.
4. If RTC-mode is not used then the following combinations are approved:
   - vdda_rtc can be combined with vdds18v
   - vdd_rtc can be combined with vdd
   - vddshv5 can be combined with other 1.8V or 3.3V vddshvn rails
   If combinations listed above are not followed then sequencing for these 3 voltage rails should follow the RTC mode timing requirements.
5. vdd_mpu, vdd_gpu, vdd_dsp, vdd_iva can be ramped at the same time or can be staggered.
6. vdd must ramp after or at the same time as vdd_mpu, vdd_gpu, vdd_dsp and vdd_iva.
7. If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v. vddshv[1-7,9-11] is allowed to ramp down at either of the two points shown in the timing diagram in either 1.8V mode or in 3.3V mode. If vddshv[1-7,9-11] ramps down at the later time in the diagram then the board design must guarantee that the vddshv[1-7,9-11] rail is never higher than 2.0 V above the vdds18v rail.
8. vddshv8 is separated out to show support for dual voltage. If a dedicated LDO/supply source is used for vddshv8, then vddshv8 ramp down should occur at one of the two earliest points in the timing diagram. If vddshv8 is powered by the same supply source as the other vddshvn rails, then it is allowed to ramp down at either of the last two points in the timing diagram.

Figure 5-7 describes vddshv[1-7,9-11] Supplies Falling Before vdds18v Supplies Delta.

Figure 5-7 vddshv* Supplies Falling After vdds18v Supplies Delta

1. Vdelta MAX = 2V
2. If vddshv8 is powered by the same supply source as the other vddshv[1-7,9-11] rails.