ZHCSJC6F March 2016 – June 2018 TDA2E
PRODUCTION DATA.
TI only supports board designs using DDR3 memory that follow the guidelines in this document. The switching characteristics and timing diagram for the DDR3 memory controller are shown in Table 8-24 and Figure 8-36.
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
1 | tc(DDR_CLK) | Cycle time, DDR_CLK | 1.5 | 2.5(1) | ns |