2 修订历史记录
Changes from March 1, 2018 to June 7, 2018 (from E Revision (March 2018) to F Revision)
- 在以下位置将引用的“ARM”更新为“Arm”:Section 1.1特性Go
- Updated "ARM" references to "Arm" in Table 3-1, Device ComparisonGo
- Added missing balls in Table 4-1, Unused Balls Specific Connection RequirementsGo
- Updated "ARM" references to "Arm" in Table 4-29, INTC Signal DescriptionsGo
- Added table note for maximum valid input voltage on an IO pin to Section 5.1, Absolute Maximum RatingsGo
- Removed voltage high level limits from CSI2 ULPS state in Table 5-14, LVCMOS CSI2 DC Electrical CharacteristicsGo
- Added references to notes under Table 5-14, LVCMOS CSI2 DC Electrical CharacteristicsGo
- Updated resetn timing in power and reset sequencing. Added clarification on the limits of resetn timing during the power/clock/reset sequence diagrams (Figure 5-2, Figure 5-5) and their footnotesGo
- Updated DPLL type A CLKOUT output frequencyGo
- Removed duplicated IOSETs from Table 7-5, VIN2 IOSETsGo
- Added new DPI VOUT Switching Characteristics tables as well as their associated MANUAL4 and MANUAL5 IO delays Go
- Updated phase polarity in all QSPI timing figuresGo
- Updated IOSET2 MUX in Table 7-63, USB3 IOSETsGo
- Added CAN delay time receive and transmit parameters in relation to the shift registers Go
- Updated "ARM" references to "Arm" in Table 7-134, Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCKGo
- Added new parameter in Table 8-23, Length Mismatch Guidelines for CSI-2 (1.5 Gbps)Go
- Updated "ARM" references to "Arm" in section TrademarksGo