ZHCSE74C September 2015 – May 2025 LMK61E2
PRODUCTION DATA
IEEE802.3 dictates that Ethernet frames stay compliant to the standard specifications when clocked with a reference clock that is within ±100ppm of the nominal frequency. In the worst case, an RX node with the local reference clock at –100ppm from the nominal frequency must be able to work seamlessly with a TX node that has a dedicated local reference clock at +100ppm from the nominal frequency. Without any clock compensation on the RX node, the read pointer severely lags behind the write pointer and cause FIFO overflow errors. On the contrary, when the local clock of the RX node operates at +100ppm from the nominal frequency and the local clock of the TX node operates at –100ppm from the nominal frequency, FIFO underflow errors occur without any clock compensation.
To prevent such overflow and underflow errors from occurring, modern ASICs and FGPAs include a clock compensation scheme that introduces elastic buffers. Such a system, shown in Figure 9-2, is validated thoroughly during the validation phase by interfacing slower nodes with faster ones and verifying compliance to IEEE802.3. The LMK61E2 provides the ability to fine tune the frequency of the outputs based on changing the load capacitance for the integrated oscillator. This fine tuning can be done through I2C as described in Integrated Oscillator. The change in load capacitance is implemented in a manner such that the output of LMK61E2 undergoes a smooth monotonic change in frequency.