ZHCSLS8 August   2020 DRV5825P

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
      1. 6.7.1 Bridge Tied Load (BTL) Configuration
      2. 6.7.2 Parallel Bridge Tied Load (PBTL) Configuration
  7. 7 Typical Characteristics
    1. 7.1 Bridge Tied Load (BTL) Configuration
    2. 7.2 Parallel Bridge Tied Load (PBTL) Configuration
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supplies
      2. 8.3.2 Device Clocking
      3. 8.3.3 Serial Audio Port – Clock Rates
      4. 8.3.4 Clock Halt Auto-recovery
      5. 8.3.5 Sample Rate on the Fly Change
      6. 8.3.6 Serial Audio Port - Data Formats and Bit Depths
      7. 8.3.7 Digital Audio Processing
      8. 8.3.8 Class D Audio Amplifier
        1. 8.3.8.1 Speaker Amplifier Gain Select
        2. 8.3.8.2 Class D Loop Bandwidth and Switching Frequency Setting
    4. 8.4 Device Functional Modes
      1. 8.4.1 Software Control
      2. 8.4.2 Speaker Amplifier Operating Modes
        1. 8.4.2.1 BTL Mode
        2. 8.4.2.2 PBTL Mode
      3. 8.4.3 Low EMI Modes
        1. 8.4.3.1 Spread Spectrum
        2. 8.4.3.2 Channel to Channel Phase Shift
        3. 8.4.3.3 Multi-Devices PWM Phase Synchronization
          1. 8.4.3.3.1 Phase Synchronization With I2S Clock In Startup Phase
          2. 8.4.3.3.2 Phase Synchronization With GPIO
      4. 8.4.4 Device State Control
      5. 8.4.5 Device Modulation
    5. 8.5 Programming and Control
      1. 8.5.1 I2C Serial Communication Bus
      2. 8.5.2 I2C Slave Address
        1. 8.5.2.1 Random Write
        2. 8.5.2.2 Sequential Write
        3. 8.5.2.3 Random Read
        4. 8.5.2.4 Sequential Read
        5. 8.5.2.5 DSP Memory Book, Page and BQ update
        6. 8.5.2.6 Checksum
          1. 8.5.2.6.1 Cyclic Redundancy Check (CRC) Checksum
          2. 8.5.2.6.2 Exclusive or (XOR) Checksum
      3. 8.5.3 Control via Software
        1. 8.5.3.1 Startup Procedures
        2. 8.5.3.2 Shutdown Procedures
        3. 8.5.3.3 Protection and Monitoring
          1. 8.5.3.3.1 Overcurrent Limit (Cycle-By-Cycle)
          2. 8.5.3.3.2 Overcurrent Shutdown (OCSD)
          3. 8.5.3.3.3 DC Detect
    6. 8.6 Register Maps
      1. 8.6.1 CONTROL PORT Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 LC Filter Design For Piezo Speaker Driving
        1. 9.1.1.1 LC Filter Recommendation
      2. 9.1.2 Bootstrap Capacitors
      3. 9.1.3 Power Supply Decoupling
      4. 9.1.4 Output EMI Filtering
    2. 9.2 Typical Applications
      1. 9.2.1 2.0 (Stereo BTL) System
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design procedures
        1. 9.2.3.1 Step One: Hardware Integration
        2. 9.2.3.2 Step Two: Hardware Integration
        3. 9.2.3.3 Step Three: Software Integration
      4. 9.2.4 MONO (PBTL) Systems
  10. 10Power Supply Recommendations
    1. 10.1 DVDD Supply
    2. 10.2 PVDD Supply
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 General Guidelines for Audio Amplifiers
      2. 11.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 11.1.3 Optimizing Thermal Performance
        1. 11.1.3.1 Device, Copper, and Component Layout
        2. 11.1.3.2 Stencil Pattern
          1. 11.1.3.2.1 PCB footprint and Via Arrangement
          2. 11.1.3.2.2 Solder Stencil
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary

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6.5 Electrical Characteristics

Free-air room temperature 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL I/O
|IIH| Input logic high current level for DVDD referenced digital input pins VIN(DigIn) = VDVDD 10 µA
|IIL| Input logic low current level for DVDD referenced digital input pins VIN(DigIn) = 0 V –10 µA
VIH(Digin) Input logic high threshold for DVDD referenced digital inputs 70% VDVDD
VIL(Digin) Input logic low threshold for DVDD referenced digital inputs 30% VDVDD
VOH(Digin) Output logic high voltage level IOH = 4 mA 80% VDVDD
VOL(Digin) Output logic low voltage level IOH = –4 mA 20% VDVDD
I2C CONTROL PORT
CL(I2C) Allowable load capacitance for each I2C Line 400 pF
fSCL(fast) Support SCL frequency No wait states, fast mode 400 kHz
fSCL(slow) Support SCL frequency No wait states, slow mode 100 kHz
SERIAL AUDIO PORT
tDLY Required LRCK/FS to SCLK rising edge delay 5 ns
DSCLK Allowable SCLK duty cycle 40% 60%
fS Supported input sample rates 32 96 kHz
fSCLK Supported SCLK frequencies 32 64 fS
fSCLK SCLK frequency 24.576 MHz
SPEAKER AMPLIFIER (ALL OUTPUT CONFIGURATIONS)
toff Turn-off Time Excluding volume ramp 10 ms
ICC Quiescent supply current of DVDD PDN=2V,DVDD=3.3V,Play mode, Piezo Drive Alolgorithm Enable,48kHz 17.5 mA
ICC Quiescent supply current of DVDD PDN=2V,DVDD=3.3V,Sleep mode 0.87 mA
ICC Quiescent supply current of DVDD PDN=2V,DVDD=3.3V,Deep Sleep mode 0.82 mA
ICC Quiescent supply current of DVDD PDN=0.8V,DVDD=3.3V,Shutdown mode 7.4 uA
ICC Quiescent supply current of PVDD PDN=2V, PVDD=24V, No Load, LC filter = 10uH + 0.47uF, Fsw = 768kHz, Output Hiz Mode 10.9 mA
ICC Quiescent supply current of PVDD PDN=2V, PVDD=24V, No Load, LC filter = 10uH + 0.47uF, Fsw = 768kHz, Sleep Mode 7.3 mA
ICC Quiescent supply current of PVDD PDN=2V, PVDD=13.5V, No Load, LC filter = 10uH + 0.47uF, Fsw = 768khz, Deep Sleep Mode 12.01 uA
ICC Quiescent supply current of PVDD PDN=0.8V, PVDD=13.5V, No Load, LC filter = 10uH + 0.47uF, Fsw = 768khz, Shutdown Mode 7.8 uA
AV(SPK_AMP) Programmable Gain Value represents the "peak voltage" disregarding clipping due to lower PVDD).
Measured at 0 dB input (1FS)		 4.87 29.5 V
ΔAV(SPK_AMP) Amplifier gain error Gain = 29.5 Vp 0.5 dB
fSPK_AMP Switching frequency of the speaker amplifier 768 kHz
RDS(on) Drain-to-source on resistance of the individual output MOSFETs FET + Metallization. 90 mΩ
OCETHRES Over-Current Error Threshold Any short to supply, ground, or other channels, BTL Mode 7 7.5 A
Over-Current cycle-by-cycle limit BTL Mode 6 6.5 A
Over-Current Error Threshold Any short to supply, ground, or other channels, PBTL Mode 14 15 A
OVETHRES(PVDD PVDD over voltage error threshold 28 V
UVETHRES(PVDD PVDD under voltage error threshold 4.2 V
OTETHRES Over temperature error threshold 160 °C
OTEHystersis Over temperature error hysteresis 10 °C
OTWTHRES Over temperature warning level 1 Read by register 0x73 bit0 112 °C
OTWTHRES Over temperature warning level 2 Read by register 0x73 bit1 122 °C
OTWTHRES Over temperature warning level 3 Read by register 0x73 bit2 134 °C
OTWTHRES Over temperature warning level 4 Read by register 0x73 bit3 146 °C
SPEAKER AMPLIFIER (STEREO BTL)
|VOS| Amplifier offset voltage Measured differentially with zero input data, programmable gain configured with 29.5 Vp/FS gain, VPVDD = 24 V –5 5 mV
ICN(SPK) Idle channel noise(A-weighted, AES17) VPVDD = 24 V, LC-filter, BD Modualtion 45 µVrms
DR Dynamic Range A-Weighted, -60dBFS method, PVDD=24V, SPK_GAIN=29.5VP/FS 111 dB
SNR Signal-to-noise ratio A-Weighted, referenced to 1% THD+N Output Level, PVDD = 24 V 111 dB
KSVR Power supply rejection ratio Injected Noise = 1 KHz, 1 Vrms, PVDD = 14.4 V, input audio signal = digital zero 72 dB
X-talkSPK Cross-talk (worst case between left-to-right and right-to-left coupling) f = 1 KHz 100 dB
SPEAKER AMPLIFIER (MONO PBTL)
|VOS| Amplifier offset voltage Measured differentially with zero input data, programmable gain configured with 29.5 Vp gain, VPVDD = 24 V -7.5 7.5 mV
DR Dynamic range A-Weighted, -60 dBFS method, PVDD=19V 109 dB
SNR Signal-to-noise ratio A-Weighted, referenced to 1% THD+N Output Level, PVDD = 19 V 109 dB
A-Weighted, referenced to 1% THD+N Output Level, PVDD = 24 V 111 dB