ZHCSLS8 August 2020 DRV5825P
PRODUCTION DATA
DRV5825P supports LRCLK(FS) rate on the fly change. For example, change LCRLK from 32kHz to 48kHz or 96kHz, Host processor needs to put the LRCLK(FS)/SCLK to Halt state at least 10ms before changing to the new sample rate.