ZHCSLS8 August   2020 DRV5825P

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
      1. 6.7.1 Bridge Tied Load (BTL) Configuration
      2. 6.7.2 Parallel Bridge Tied Load (PBTL) Configuration
  7. 7 Typical Characteristics
    1. 7.1 Bridge Tied Load (BTL) Configuration
    2. 7.2 Parallel Bridge Tied Load (PBTL) Configuration
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supplies
      2. 8.3.2 Device Clocking
      3. 8.3.3 Serial Audio Port – Clock Rates
      4. 8.3.4 Clock Halt Auto-recovery
      5. 8.3.5 Sample Rate on the Fly Change
      6. 8.3.6 Serial Audio Port - Data Formats and Bit Depths
      7. 8.3.7 Digital Audio Processing
      8. 8.3.8 Class D Audio Amplifier
        1. 8.3.8.1 Speaker Amplifier Gain Select
        2. 8.3.8.2 Class D Loop Bandwidth and Switching Frequency Setting
    4. 8.4 Device Functional Modes
      1. 8.4.1 Software Control
      2. 8.4.2 Speaker Amplifier Operating Modes
        1. 8.4.2.1 BTL Mode
        2. 8.4.2.2 PBTL Mode
      3. 8.4.3 Low EMI Modes
        1. 8.4.3.1 Spread Spectrum
        2. 8.4.3.2 Channel to Channel Phase Shift
        3. 8.4.3.3 Multi-Devices PWM Phase Synchronization
          1. 8.4.3.3.1 Phase Synchronization With I2S Clock In Startup Phase
          2. 8.4.3.3.2 Phase Synchronization With GPIO
      4. 8.4.4 Device State Control
      5. 8.4.5 Device Modulation
    5. 8.5 Programming and Control
      1. 8.5.1 I2C Serial Communication Bus
      2. 8.5.2 I2C Slave Address
        1. 8.5.2.1 Random Write
        2. 8.5.2.2 Sequential Write
        3. 8.5.2.3 Random Read
        4. 8.5.2.4 Sequential Read
        5. 8.5.2.5 DSP Memory Book, Page and BQ update
        6. 8.5.2.6 Checksum
          1. 8.5.2.6.1 Cyclic Redundancy Check (CRC) Checksum
          2. 8.5.2.6.2 Exclusive or (XOR) Checksum
      3. 8.5.3 Control via Software
        1. 8.5.3.1 Startup Procedures
        2. 8.5.3.2 Shutdown Procedures
        3. 8.5.3.3 Protection and Monitoring
          1. 8.5.3.3.1 Overcurrent Limit (Cycle-By-Cycle)
          2. 8.5.3.3.2 Overcurrent Shutdown (OCSD)
          3. 8.5.3.3.3 DC Detect
    6. 8.6 Register Maps
      1. 8.6.1 CONTROL PORT Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 LC Filter Design For Piezo Speaker Driving
        1. 9.1.1.1 LC Filter Recommendation
      2. 9.1.2 Bootstrap Capacitors
      3. 9.1.3 Power Supply Decoupling
      4. 9.1.4 Output EMI Filtering
    2. 9.2 Typical Applications
      1. 9.2.1 2.0 (Stereo BTL) System
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design procedures
        1. 9.2.3.1 Step One: Hardware Integration
        2. 9.2.3.2 Step Two: Hardware Integration
        3. 9.2.3.3 Step Three: Software Integration
      4. 9.2.4 MONO (PBTL) Systems
  10. 10Power Supply Recommendations
    1. 10.1 DVDD Supply
    2. 10.2 PVDD Supply
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 General Guidelines for Audio Amplifiers
      2. 11.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 11.1.3 Optimizing Thermal Performance
        1. 11.1.3.1 Device, Copper, and Component Layout
        2. 11.1.3.2 Stencil Pattern
          1. 11.1.3.2.1 PCB footprint and Via Arrangement
          2. 11.1.3.2.2 Solder Stencil
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary

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9.1.1.1 LC Filter Recommendation

LC filter selection recommendation principles show as below::

  1. Make sure fResonance > 25 kHz for over current avoidance and peaking voltage protection. The Max inductance of Inductor is limited by the fResonance > 25 kHz. fResonance = 1/(2×π×(L×(C+2×Cpiezo))^0.5)
  2. Larger inductor means larger DCR (better stability) and smaller startup/ripple current.
  3. Larger inductor, smaller fResonance, more loop gain margin, better stability.
  4. Some corner consideration:
    • Inductor variation and DCR variation. Suggest to keep within +/-10% make sure fResonance > 25 kHz.
    • Make sure DCR of inductor larger than 25 mΩ.
    • Piezo speaker capacitance variation. Also make sure fResonance > 25 kHz.
    Table 9-1 LC Filter recommendation
    Piezo Speaker Capacitance Fsw (Switching Frequency) Class D Loop Bandwidth (kHz) LC Filter Recommendation Resonance Frequency
    0.6 µF 768kHz 175kHz 8.2 µH (DCR ≥ 25 mΩ) +0.47 µF 43.4 kHz
    10 µH (DCR ≥ 25 mΩ) + 0.68 µF 36.9 kHz
    15 µH (DCR ≥ 25 mΩ) + 0.47 µF 32 kHz
    22 µH (DCR ≥ 25 mΩ) + 0.4 7µF 26.4 kHz
    1 µF 8.2 µH (DCR ≥ 25 mΩ) +0.47 µF 35.1 kHz
    10 µH (DCR ≥ 25 mΩ) + 0.68 µF 30.5 kHz
    15 µH (DCR ≥ 25 mΩ) + 0.47 µF 26 kHz
    2 µF 4.7 µH (DCR ≥ 25 mΩ) +0.47 µF 34.7 kHz
    8.2 µH (DCR ≥ 25 mΩ) +0.47 µF 26.3 kHz
    4.5 µF 3.3 µH (DCR ≥ 25 mΩ) +0.47 µF 28 kHz