The PCB footprint (also known as a symbol or land pattern) communicates to the PCB fabrication vendor the shape and position of the copper patterns to which the DRV5825P device is soldered. This footprint can be followed directly from the guidance in the package addendum at the end of this data sheet. It is important to make sure that the thermal pad, which connects electrically and thermally to the PowerPAD™ of the DRV5825P device, be made no smaller than what is specified in the package addendum. This ensures that the DRV5825P device has the largest interface possible to move heat from the device to the board.

The via pattern shown in the package addendum provides an improved interface to carry the heat from the device through to the layers of the PCB, because small diameter plated vias (with minimally-sized annular rings) present a low thermal-impedance path from the device into the PCB. Once into the PCB, the heat travels away from the device and into the surrounding structures and air. By increasing the number of vias, as shown in the Section 11.2 section, this interface can benefit from improved thermal performance.

More notes on the construction and placement of vias are as follows:

• Remove thermal reliefs on thermal vias, because they impede the flow of heat through the via.
• Vias filled with thermally conductive material are best, but a simple plated via can be used to avoid the additional cost of filled vias.
• The diameter of the drull must be 8 mm or less. Also, the distance between the via barrel and the surrounding planes should be minimized to help heat flow from the via into the surrounding copper material. In all cases, minimum spacing should be determined by the voltages present on the planes surrounding the via and minimized wherever possible.
• Vias should be arranged in columns, which extend in a line radially from the heat source to the surrounding area. This arrangement is shown in the Section 11.2 section.
• Ensure that vias do not cut off power current flow from the power supply through the planes on internal layers. If needed, remove some vias that are farthest from the DRV5825P device to open up the current path to and from the device.