ZHCSNH1C May   2021  – November 2022 DLPC6540

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  DMD HSSI Electrical Characteristics
    8. 6.8  DMD Low-Speed LVDS Electrical Characteristics
    9. 6.9  V-by-One Interface Electrical Characteristics
    10. 6.10 USB Electrical Characteristics
    11. 6.11 System Oscillator Timing Requirements
    12. 6.12 Power Supply and Reset Timing Requirements
    13. 6.13 DMD HSSI Timing Requirements
    14. 6.14 DMD Low-Speed LVDS Timing Requirements
    15. 6.15 V-by-One Interface General Timing Requirements
    16. 6.16 Source Frame Timing Requirements
    17. 6.17 Synchronous Serial Port Interface Timing Requirements
    18. 6.18 Master and Slave I2C Interface Timing Requirements
    19. 6.19 Programmable Output Clock Timing Requirements
    20. 6.20 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
    21. 6.21 JTAG ARM Multi-Ice Interface Timing Requirements (Debug Only)
    22. 6.22 Multi-Trace ETM Interface Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Sources
      2. 7.3.2 Processing Delays
      3. 7.3.3 V-by-One Interface
      4. 7.3.4 DMD (HSSI) Interface
      5. 7.3.5 Program Memory Flash Interface
      6. 7.3.6 GPIO Supported Functionality
      7. 7.3.7 Debug Support
    4. 7.4 Device Operational Modes
      1. 7.4.1 Standby Mode
      2. 7.4.2 Active Mode
        1. 7.4.2.1 Normal Configuration
  8. 8 Power Supply Recommendations
    1. 8.1 Power Supply Management
    2. 8.2 Hot Plug Usage
    3. 8.3 Power Supplies for Unused Input Source Interfaces
    4. 8.4 Power Supplies
      1. 8.4.1 1.15-V Power Supplies
      2. 8.4.2 1.21V Power Supply
      3. 8.4.3 1.8-V Power Supplies
      4. 8.4.4 3.3-V Power Supplies
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 General Layout Guidelines
      2. 9.1.2 Power Supply Layout Guidelines
      3. 9.1.3 Layout Guidelines for Internal Controller PLL Power
      4. 9.1.4 Layout Guideline for DLPC6540 Reference Clock
        1. 9.1.4.1 Recommended Crystal Oscillator Configuration
      5. 9.1.5 V-by-One Interface Layout Considerations
      6. 9.1.6 USB Interface Layout Considerations
      7. 9.1.7 DMD Interface Layout Considerations
      8. 9.1.8 General Handling Guidelines for Unused CMOS-Type Pins
      9. 9.1.9 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
    2. 9.2 Thermal Considerations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 第三方产品免责声明
      2. 10.1.2 Device Nomenclature
        1. 10.1.2.1 Device Markings
        2. 10.1.2.2 Package Data
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 术语表
      1. 10.6.1 Video Timing Parameter Definitions
  11. 11Mechanical, Packaging, and Orderable Information
    1.     79

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6.19 Programmable Output Clock Timing Requirements

PARAMETER MIN MAX UNIT
fclockClock frequency, OCLKA (1)0.1948.75MHz
tclockClock period, OCLKA20.525263.15ns
tw(H)Pulse duration high, OCLKA
(50% reference points)		(tclock/2) - 2ns
tw(L)Pulse duration low, OCLKA
(50% reference points)		(tclock/2) - 2ns
tcclkjitJitter, OCLKA200ps
fclockClock frequency, OCLKB (1)0.1948.75MHz
tclockClock period, OCLKB20.525263.15ns
tw(H)Pulse duration high, OCLKB
(50% reference points)		(tclock/2) - 2ns
tw(L)Pulse duration low, OCLKB
(50% reference points)		(tclock/2) - 2ns
tcclkjitJitter, OCLKB200ps
fclockClock frequency, OCLKC (1)0.1948.75MHz
tclockClock period, OCLKC20.525263.15ns
tw(H)Pulse duration high, OCLKC
(50% reference points)		(tclock/2) - 2ns
tw(L)Pulse duration low, OCLKC
(50% reference points)		(tclock/2) - 2ns
tcclkjitJitter, OCLKC200ps
fclockClock frequency, OCLKD (1)0.1948.75MHz
tclockClock period, OCLKD20.525263.15ns
tw(H)Pulse duration high, OCLKD
(50% reference points)		(tclock/2) - 2ns
tw(L)Pulse duration low, OCLKD
(50% reference points)		(tclock/2) - 2ns
tcclkjitJitter, OCLKD200ps
(1)
  1. OCLKA is a dedicated pin, while OCLKB thru OCLKD are available via GPIO as alternate functions.
  2. The frequency of OCLKA thru OCLKD is programmable, with each having a power-up default frequency of 0.77 MHz. This default frequency is not that meaningful for OCLKB thru OCLKD since they must be configured to their alternate GPIO function before they can be used as a clock output.