ZHCSNH1C May   2021  – November 2022 DLPC6540

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  DMD HSSI Electrical Characteristics
    8. 6.8  DMD Low-Speed LVDS Electrical Characteristics
    9. 6.9  V-by-One Interface Electrical Characteristics
    10. 6.10 USB Electrical Characteristics
    11. 6.11 System Oscillator Timing Requirements
    12. 6.12 Power Supply and Reset Timing Requirements
    13. 6.13 DMD HSSI Timing Requirements
    14. 6.14 DMD Low-Speed LVDS Timing Requirements
    15. 6.15 V-by-One Interface General Timing Requirements
    16. 6.16 Source Frame Timing Requirements
    17. 6.17 Synchronous Serial Port Interface Timing Requirements
    18. 6.18 Master and Slave I2C Interface Timing Requirements
    19. 6.19 Programmable Output Clock Timing Requirements
    20. 6.20 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
    21. 6.21 JTAG ARM Multi-Ice Interface Timing Requirements (Debug Only)
    22. 6.22 Multi-Trace ETM Interface Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Sources
      2. 7.3.2 Processing Delays
      3. 7.3.3 V-by-One Interface
      4. 7.3.4 DMD (HSSI) Interface
      5. 7.3.5 Program Memory Flash Interface
      6. 7.3.6 GPIO Supported Functionality
      7. 7.3.7 Debug Support
    4. 7.4 Device Operational Modes
      1. 7.4.1 Standby Mode
      2. 7.4.2 Active Mode
        1. 7.4.2.1 Normal Configuration
  8. 8 Power Supply Recommendations
    1. 8.1 Power Supply Management
    2. 8.2 Hot Plug Usage
    3. 8.3 Power Supplies for Unused Input Source Interfaces
    4. 8.4 Power Supplies
      1. 8.4.1 1.15-V Power Supplies
      2. 8.4.2 1.21V Power Supply
      3. 8.4.3 1.8-V Power Supplies
      4. 8.4.4 3.3-V Power Supplies
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 General Layout Guidelines
      2. 9.1.2 Power Supply Layout Guidelines
      3. 9.1.3 Layout Guidelines for Internal Controller PLL Power
      4. 9.1.4 Layout Guideline for DLPC6540 Reference Clock
        1. 9.1.4.1 Recommended Crystal Oscillator Configuration
      5. 9.1.5 V-by-One Interface Layout Considerations
      6. 9.1.6 USB Interface Layout Considerations
      7. 9.1.7 DMD Interface Layout Considerations
      8. 9.1.8 General Handling Guidelines for Unused CMOS-Type Pins
      9. 9.1.9 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
    2. 9.2 Thermal Considerations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 第三方产品免责声明
      2. 10.1.2 Device Nomenclature
        1. 10.1.2.1 Device Markings
        2. 10.1.2.2 Package Data
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 术语表
      1. 10.6.1 Video Timing Parameter Definitions
  11. 11Mechanical, Packaging, and Orderable Information
    1.     79

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6.17 Synchronous Serial Port Interface Timing Requirements

For SSP0, SSP1 and SSP2(1)(2)
PARAMETERMINMAXUNIT
SSP Master
fclockClock frequency, SSPx_CLK
50% to 50% reference points0.3839.0MHz
tclockClock Period, SSPx_CLK50% to 50% reference points25.63632ns
tw(L)Pulse duration low, SSPx_CLK
50% to 50% reference points12.0ns
tw(H)Pulse duration high, SSPx_CLK
50% to 50% reference points12.0ns
tdelayOutput Delay – SSPx_TXD (MOSI)
-2.52.5ns
tsuSetup time – SSPx_RXD (MISO)
50% to 50% reference points15.0ns
thhold time – SSPx_RXD (MISO)
50% to 50% reference points0ns
ttTransition time (tr and tf- SSPx_RXD20% to 80% reference points1.5ns
tclkjitClock Jitter, SSPx_CLK300ps
tdelay∆Clock output delay ∆ { | tw(H) - tw(L) | }500ps
SSP Slave
tdelayOutput Delay – SSPx_TXD (MOSI)
015ns
tsuSetup time – SSPx_RXD (MISO)
50% to 50% reference points2.5ns
thhold time – SSPx_RXD (MISO)
50% to 50% reference points2.5ns
(1) The DLPC6540 SPI interfaces support SPI Modes 0, 1, 2, and 3 (that is, both clock polarities and both clock phases) as shown in Table 6-2 and Figure 6-15. As such, each SPI interface configuration must be setup to match the SPI mode being used.
(2) In most SPI applications, one clock edge is used by both master and slave devices for transmitting data while the other edge is use by both for sampling received data. This is referred to as Standard SPI Protocol. To maximize the SPI_CLK frequency potential, SPI masters can alternatively be designed to sample the data in (MISO) bit on the same clock edge used to transmit the next data out (MOSI) bit. This is referred to as Enhanced SPI Protocol. The DLPC6540 SPI master implementation supports both protocols (part of SPI interface configuration), however, to be able to use the "Enhanced SPI Protocol", the slave device must meet the requirement shown in Figure 6-16.
Table 6-2 SPI Clocking Modes
SPI Clocking ModeSPI Clock PolaritySPI Clock Phase
000
101
210
311
GUID-E3A09DBB-2938-457A-BFFD-F6FFDC424C8A-low.gifFigure 6-15 Timing Diagram for SPI Clocking Modes
GUID-EEEE1700-48A6-406B-86E7-07EA5CEDB49A-low.gifFigure 6-16 Requirement for Enhanced SPI Protocol
GUID-DEFAF8AC-7A53-44BF-8EBE-4ABEB7349399-low.gifFigure 6-17 Timing Diagram for SSP Master (Modes 0/3)