ZHCSNH1C May   2021  – November 2022 DLPC6540

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  DMD HSSI Electrical Characteristics
    8. 6.8  DMD Low-Speed LVDS Electrical Characteristics
    9. 6.9  V-by-One Interface Electrical Characteristics
    10. 6.10 USB Electrical Characteristics
    11. 6.11 System Oscillator Timing Requirements
    12. 6.12 Power Supply and Reset Timing Requirements
    13. 6.13 DMD HSSI Timing Requirements
    14. 6.14 DMD Low-Speed LVDS Timing Requirements
    15. 6.15 V-by-One Interface General Timing Requirements
    16. 6.16 Source Frame Timing Requirements
    17. 6.17 Synchronous Serial Port Interface Timing Requirements
    18. 6.18 Master and Slave I2C Interface Timing Requirements
    19. 6.19 Programmable Output Clock Timing Requirements
    20. 6.20 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
    21. 6.21 JTAG ARM Multi-Ice Interface Timing Requirements (Debug Only)
    22. 6.22 Multi-Trace ETM Interface Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Sources
      2. 7.3.2 Processing Delays
      3. 7.3.3 V-by-One Interface
      4. 7.3.4 DMD (HSSI) Interface
      5. 7.3.5 Program Memory Flash Interface
      6. 7.3.6 GPIO Supported Functionality
      7. 7.3.7 Debug Support
    4. 7.4 Device Operational Modes
      1. 7.4.1 Standby Mode
      2. 7.4.2 Active Mode
        1. 7.4.2.1 Normal Configuration
  8. 8 Power Supply Recommendations
    1. 8.1 Power Supply Management
    2. 8.2 Hot Plug Usage
    3. 8.3 Power Supplies for Unused Input Source Interfaces
    4. 8.4 Power Supplies
      1. 8.4.1 1.15-V Power Supplies
      2. 8.4.2 1.21V Power Supply
      3. 8.4.3 1.8-V Power Supplies
      4. 8.4.4 3.3-V Power Supplies
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 General Layout Guidelines
      2. 9.1.2 Power Supply Layout Guidelines
      3. 9.1.3 Layout Guidelines for Internal Controller PLL Power
      4. 9.1.4 Layout Guideline for DLPC6540 Reference Clock
        1. 9.1.4.1 Recommended Crystal Oscillator Configuration
      5. 9.1.5 V-by-One Interface Layout Considerations
      6. 9.1.6 USB Interface Layout Considerations
      7. 9.1.7 DMD Interface Layout Considerations
      8. 9.1.8 General Handling Guidelines for Unused CMOS-Type Pins
      9. 9.1.9 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
    2. 9.2 Thermal Considerations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 第三方产品免责声明
      2. 10.1.2 Device Nomenclature
        1. 10.1.2.1 Device Markings
        2. 10.1.2.2 Package Data
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 术语表
      1. 10.6.1 Video Timing Parameter Definitions
  11. 11Mechanical, Packaging, and Orderable Information
    1.     79

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9.1.4.1 Recommended Crystal Oscillator Configuration

Table 9-2 Recommended Crystal Configurations
PARAMETER CRYSTAL A CRYSTAL B UNIT
Crystal circuit configuration Parallel resonant Parallel resonant
Crystal type Fundamental (first harmonic) Fundamental (first harmonic)
Crystal nominal frequency 40 38 MHz
Crystal frequency tolerance (1) ±100 (200 p-p max) ±100 (200 p-p max) PPM
Crystal equivalent series resistance (ESR) 60 (Max) 60 (Max) Ω
Crystal load capacitance 20 (Max) 20 (Max) pF
Crystal Shunt Load capacitance 7 (Max) 7 (Max) pF
Temperature range –40°C to +85°C –40°C to +85°C °C
Drive level 100 (Nominal) 100 (Nominal) µW
RFB feedback resistor (nominal) 1 Meg (Nominal) 1 Meg (Nominal) Ω
CL1 external crystal load capacitor See equation in (2). See equation in (2). pF
CL2 external crystal load capacitor See equation in (3). See equation in (3). pF
PCB layout A ground isolation ring around the crystal is recommended. A ground isolation ring around the crystal is recommended.
(1) Crystal frequency tolerance to include accuracy, temperature, aging, and trim sensitivity. These are typically specified separately and the sum of all required to meet this requirement.
(2) CL1 = 2 × (CL – Cstray_pll_refclk_i), where: Cstray_pll_refclk_i = Sum of package and PCB stray capacitance at the crystal pin associated with the Controller pin REFCLKx_I. See Table 9-3.
(3) CL2 = 2 × (CL – Cstray_pll_refclk_o), where: Cstray_pll_refclk_o = Sum of package and PCB stray capacitance at the crystal pin associated with the Controller pin REFCLKx_O. See Table 9-3.
Table 9-3 Crystal Pin Capacitance
PARAMETER MIN NOM MAX UNITS
Cstray_pll_refclkA_i Sum of package and PCB stray capacitance at REFCLKA_I 4.5 pF
Cstray_pll_refclkA_o Sum of package and PCB stray capacitance at REFCLKA_O 4.5 pF
Cstray_pll_refclkB_i Sum of package and PCB stray capacitance at REFCLKB_I 4.5 pF
Cstray_pll_refclkB_o Sum of package and PCB stray capacitance at REFCLKB_O 4.5 pF

The crystal circuits in the DLPC6540 have dedicated power (VAD33_OSCA and VAD33_OSCB) pins, with the recommended filtering for each shown in Figure 9-11, and recommended values shown in Table 9-1.

GUID-6AD3ABB7-DC24-4922-9D7F-4EB3DA9EBD72-low.gif Figure 9-11 Crystal Power Supply Filtering
Table 9-4 DLPC6540 Recommended Crystal Parts
MANUFACTURER PART NUMBER NOMINAL FREQUENCY FREQUENCY TOLERANCE,
FREQUENCY STABILITY,
AGING/YEAR		 ESR LOAD CAPACITANCE OPERATING TEMPERATURE DRIVE LEVEL
TXC 7M38070001 (1) 38 MHz Freq Tolerance:
±20 ppm		 30-Ω max 12 pF –40°C to +85°C 100 µW
Freq Stability:
±20 ppm
Aging/Year: ±3 ppm
TXC 7M40070041 (2) 40 MHz Freq Tolerance:
±20 ppm		 30-Ω max 12 pF –40°C to +85°C 100 µW
Freq Stability:
±20 ppm
Aging/Year: ±3 ppm
(1) This device requires an RS resistor with value = 0.
(2) This device requires an RS resistor with value = 0.