ZHCSNH1C May   2021  – November 2022 DLPC6540

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  DMD HSSI Electrical Characteristics
    8. 6.8  DMD Low-Speed LVDS Electrical Characteristics
    9. 6.9  V-by-One Interface Electrical Characteristics
    10. 6.10 USB Electrical Characteristics
    11. 6.11 System Oscillator Timing Requirements
    12. 6.12 Power Supply and Reset Timing Requirements
    13. 6.13 DMD HSSI Timing Requirements
    14. 6.14 DMD Low-Speed LVDS Timing Requirements
    15. 6.15 V-by-One Interface General Timing Requirements
    16. 6.16 Source Frame Timing Requirements
    17. 6.17 Synchronous Serial Port Interface Timing Requirements
    18. 6.18 Master and Slave I2C Interface Timing Requirements
    19. 6.19 Programmable Output Clock Timing Requirements
    20. 6.20 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
    21. 6.21 JTAG ARM Multi-Ice Interface Timing Requirements (Debug Only)
    22. 6.22 Multi-Trace ETM Interface Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Sources
      2. 7.3.2 Processing Delays
      3. 7.3.3 V-by-One Interface
      4. 7.3.4 DMD (HSSI) Interface
      5. 7.3.5 Program Memory Flash Interface
      6. 7.3.6 GPIO Supported Functionality
      7. 7.3.7 Debug Support
    4. 7.4 Device Operational Modes
      1. 7.4.1 Standby Mode
      2. 7.4.2 Active Mode
        1. 7.4.2.1 Normal Configuration
  8. 8 Power Supply Recommendations
    1. 8.1 Power Supply Management
    2. 8.2 Hot Plug Usage
    3. 8.3 Power Supplies for Unused Input Source Interfaces
    4. 8.4 Power Supplies
      1. 8.4.1 1.15-V Power Supplies
      2. 8.4.2 1.21V Power Supply
      3. 8.4.3 1.8-V Power Supplies
      4. 8.4.4 3.3-V Power Supplies
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 General Layout Guidelines
      2. 9.1.2 Power Supply Layout Guidelines
      3. 9.1.3 Layout Guidelines for Internal Controller PLL Power
      4. 9.1.4 Layout Guideline for DLPC6540 Reference Clock
        1. 9.1.4.1 Recommended Crystal Oscillator Configuration
      5. 9.1.5 V-by-One Interface Layout Considerations
      6. 9.1.6 USB Interface Layout Considerations
      7. 9.1.7 DMD Interface Layout Considerations
      8. 9.1.8 General Handling Guidelines for Unused CMOS-Type Pins
      9. 9.1.9 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
    2. 9.2 Thermal Considerations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 第三方产品免责声明
      2. 10.1.2 Device Nomenclature
        1. 10.1.2.1 Device Markings
        2. 10.1.2.2 Package Data
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 术语表
      1. 10.6.1 Video Timing Parameter Definitions
  11. 11Mechanical, Packaging, and Orderable Information
    1.     79

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7.3.6 GPIO Supported Functionality

The DLPC6540 provides 88 general purpose I/O that are available to support a variety of functions for many different product configurations. In general, most of these I/O pins support only one specific function based on a specific product configuration, although that function can be different for a different product configuration. Most of these I/O can also be made available for TI test and debug use. Each of the following GPIO tables provide product specific details on the allocated use of each of the GPIO for a specific supported product configuration.

Table 7-18 GPIO Supported Functionality - LED with DLPA3005 (1)
GPIOSIGNAL NAMEDESCRIPTION
GPIO_00SSP1_SCLK (I)SSP Master or Slave
GPIO_01SSP1_DI (I)SSP Master or Slave
GPIO_02SSP1_DO (O)SSP Master or Slave
GPIO_03SSP1_CSZ0 (I)SSP Master or Slave
GPIO_04SSP1_CSZ1 (I)SSP Master or Slave
GPIO_05SSP1_CSZ2 (I)SSP Master or Slave
GPIO_06SAS_CLK (O)
GPIO_07SAS_DI (I)
GPIO_08SAS_DO (O)
GPIO_09SAS_CSZ (O)
GPIO_10SAS_INTGTR_EN (O)
GPIO_11IIC1_SCL (B)
GPIO_12IIC1_SDA (B)
GPIO_13UART1_TXD (O)
GPIO_14UART1_RXD (I)
GPIO_15UART1_CTSZ (I)
GPIO_16UART1_RTSZ (O)
GPIO_17General Purpose Input/OutputAvailable for general host use via Host Commands
GPIO_18IR0 (I)
GPIO_19IR1 (I)
GPIO_20PWM-IN0 (I)
GPIO_21PWM-IN1 (I)
GPIO_223D LR (I)For 3D applications: Left or right 3D reference (left = 1, right = 0). To be provided by the host when a 3D command is not provided. Must transition in the middle of each frame (no closer than 1 ms to the active edge of VSYNC)
GPIO_23LL_FAULT (O)
GPIO_24LEDSEL_0 (O)
GPIO_25LEDSEL_1 (O)
GPIO_26General Purpose Input/OutputAvailable for general host use via Host Commands
GPIO_27General Purpose Input/OutputAvailable for general host use via Host Commands
GPIO_28Heartbeat (O)
GPIO_29General Purpose Input/OutputAvailable for general host use via Host Commands
GPIO_30VBIAS_MON (I)
GPIO_31HDMI_CEC (B)
GPIO_32IIC2_SCL (B)
GPIO_33IIC2_SDA (B)
GPIO_34WRP_TRIG_OUT (O)
GPIO_35DAO_DO_0 (O)
GPIO_36DAO_DO_1 (O)
GPIO_37DAO_CLKOUT (O)
GPIO_38HBT_DO (O)
GPIO_39HBT_CLKOUT (O)
GPIO_40SSP2_SCLK (I)SSP Master
GPIO_41SSP2_DI (I)SSP Master
GPIO_42SSP2_DO (O)SSP Master
GPIO_43SSP2_CSZ0 (I)SSP Master
GPIO_44SSP2_CSZ1 (I)SSP Master
GPIO_45SSP2_CSZ2 (I)SSP Master
GPIO_46General Purpose Input/OutputAvailable for general host use via Host Commands
GPIO_47PM_ADDR_23 (O)
GPIO_48USB OTG Charge Pump Enable (O)
GPIO_49SSP0_CSZ4 (O)DLPA3005
GPIO_50SSP0_CSZ3 (O)
GPIO_51General Purpose Input/OutputAvailable for general host use via Host Commands
GPIO_52LED_Enable (O)
GPIO_53General Purpose Input/OutputAvailable for general host use via Host Commands
GPIO_54General Purpose Input/OutputAvailable for general host use via Host Commands
GPIO_55General Purpose Input/OutputAvailable for general host use via Host Commands
GPIO_56General Purpose Input/OutputAvailable for general host use via Host Commands
GPIO_57General Purpose Input/OutputAvailable for general host use via Host Commands
GPIO_58I2C_BUSY (O)
GPIO_59General Purpose Input/OutputAvailable for general host use via Host Commands
GPIO_60General Purpose Input/OutputAvailable for general host use via Host Commands
GPIO_61General Purpose Input/OutputAvailable for general host use via Host Commands
GPIO_62General Purpose Input/OutputAvailable for general host use via Host Commands
GPIO_63PROJ_ON (I)
GPIO_64HOLD_BOOTZ (I)
GPIO_654 way XPR (O)
GPIO_664 way XPR (O)
GPIO_674 way XPR (O)
GPIO_684 way XPR (O)
GPIO_694 way XPR (O)
GPIO_704 way XPR (O)
GPIO_714 way XPR (O)
GPIO_724 way XPR (O)
GPIO_734 way XPR (O)
GPIO_744 way XPR (O)
GPIO_754 way XPR (O)
GPIO_764 way XPR (O)
GPIO_77General Purpose Input/OutputAvailable for general host use via Host Commands
GPIO_78General Purpose Input/OutputAvailable for general host use via Host Commands
GPIO_79General Purpose Input/OutputAvailable for general host use via Host Commands
GPIO_80General Purpose Input/OutputAvailable for general host use via Host Commands
GPIO_81General Purpose Input/OutputAvailable for general host use via Host Commands
GPIO_82General Purpose Input/OutputAvailable for general host use via Host Commands
GPIO_83General Purpose Input/OutputAvailable for general host use via Host Commands
GPIO_84General Purpose Input/OutputAvailable for general host use via Host Commands
GPIO_85General Purpose Input/OutputAvailable for general host use via Host Commands
GPIO_86General Purpose Input/OutputAvailable for general host use via Host Commands
GPIO_87General Purpose Input/OutputAvailable for general host use via Host Commands
(1) All GPIO that are listed as General Purpose Input/Output must be configured as an input, a standard output, or an open-drain output. This is set in the flash configuration. It is suggested that all unused General Purpose Input/Output GPIO should be configured as a logic zero output and be left unconnected, otherwise an external pull-up or pull-down will be required to avoid a floating input. It should be noted that the reset default for all GPIO is as an input signal. It should also be noted that an external pull-up (≤ 10kΩ) is required for each signal configured as open-drain output.