ZHCSNH1C May   2021  – November 2022 DLPC6540

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  DMD HSSI Electrical Characteristics
    8. 6.8  DMD Low-Speed LVDS Electrical Characteristics
    9. 6.9  V-by-One Interface Electrical Characteristics
    10. 6.10 USB Electrical Characteristics
    11. 6.11 System Oscillator Timing Requirements
    12. 6.12 Power Supply and Reset Timing Requirements
    13. 6.13 DMD HSSI Timing Requirements
    14. 6.14 DMD Low-Speed LVDS Timing Requirements
    15. 6.15 V-by-One Interface General Timing Requirements
    16. 6.16 Source Frame Timing Requirements
    17. 6.17 Synchronous Serial Port Interface Timing Requirements
    18. 6.18 Master and Slave I2C Interface Timing Requirements
    19. 6.19 Programmable Output Clock Timing Requirements
    20. 6.20 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
    21. 6.21 JTAG ARM Multi-Ice Interface Timing Requirements (Debug Only)
    22. 6.22 Multi-Trace ETM Interface Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Sources
      2. 7.3.2 Processing Delays
      3. 7.3.3 V-by-One Interface
      4. 7.3.4 DMD (HSSI) Interface
      5. 7.3.5 Program Memory Flash Interface
      6. 7.3.6 GPIO Supported Functionality
      7. 7.3.7 Debug Support
    4. 7.4 Device Operational Modes
      1. 7.4.1 Standby Mode
      2. 7.4.2 Active Mode
        1. 7.4.2.1 Normal Configuration
  8. 8 Power Supply Recommendations
    1. 8.1 Power Supply Management
    2. 8.2 Hot Plug Usage
    3. 8.3 Power Supplies for Unused Input Source Interfaces
    4. 8.4 Power Supplies
      1. 8.4.1 1.15-V Power Supplies
      2. 8.4.2 1.21V Power Supply
      3. 8.4.3 1.8-V Power Supplies
      4. 8.4.4 3.3-V Power Supplies
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 General Layout Guidelines
      2. 9.1.2 Power Supply Layout Guidelines
      3. 9.1.3 Layout Guidelines for Internal Controller PLL Power
      4. 9.1.4 Layout Guideline for DLPC6540 Reference Clock
        1. 9.1.4.1 Recommended Crystal Oscillator Configuration
      5. 9.1.5 V-by-One Interface Layout Considerations
      6. 9.1.6 USB Interface Layout Considerations
      7. 9.1.7 DMD Interface Layout Considerations
      8. 9.1.8 General Handling Guidelines for Unused CMOS-Type Pins
      9. 9.1.9 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
    2. 9.2 Thermal Considerations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 第三方产品免责声明
      2. 10.1.2 Device Nomenclature
        1. 10.1.2.1 Device Markings
        2. 10.1.2.2 Package Data
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 术语表
      1. 10.6.1 Video Timing Parameter Definitions
  11. 11Mechanical, Packaging, and Orderable Information
    1.     79

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9.1.6 USB Interface Layout Considerations

The DLPC6540 USB differential interface waveform quality and timing is dependent on the total length of the interconnect system, the spacing between traces, the characteristic impedance, etch losses, and how well matched the lengths are across the interface. Thus, ensuring positive timing margin requires attention to many factors.

DLPC6540 I/O timing parameters, USB transmitter and receiver timing parameters, as well as USB specific timing requirements can be found in their corresponding data sheets. PCB routing mismatch can be budgeted and met through controlled PCB routing. PCB related requirements for USB are provided in Table 9-6 as a starting point for the customer.

Table 9-6 USB Interface PBC Related Requirements (1)(2)
PARAMETERMINTYPMAXUNIT
Cross-talk between data lane (USB_DAT_P, USB_DAT_N) and other signals< 1.5mVpp
Intra-lane skew (USB_DAT_P, USB_DAT_N)< 20ps
Differential Impedance (USB_DAT_P, USB_DAT_N)76.590103.5Ω
Single Mode impedance (USB_DAT_P, USB_DAT_N)45Ω
Common Mode Impedance (USB_DAT_P, USB_DAT_N)213039Ω
Parasitic resistance (USB_DAT_P, USB_DAT_N)≤ 0.5Ω
Total capacitance (USB_DAT_P, USB_DAT_N)< 4pF
Differences of trace capacitance between USB_DAT_P, USB_DAT_N< 1pF
TXRTUNE resistor172.26174175.74Ω
(1) If using the minimum trace width and spacing to escape the Controller ball field, widening these out after escape is desirable if practical to achieve the target 100 Ω impedance (e.g. to reduce transmission line losses).
(2) One pcb layout example for the differential pair is shown in Figure 9-13

Additional layout guidelines for USB_DAT_P/USB_DAT_N:

  • Route the differential signal pairs on the top layer of the PBC to minimize the number of vias. Limit the number of necessary vias to two.
  • Route differential signal pairs over a single ground or power plane using a Micro-strip line configuration. Ground guard traces are also recommended.
  • Do not route the differential signal pairs over the slit of power or ground planes.
  • Minimize the trace length mismatch for each pair, and between each pair, in order to meet the skew requirements.
  • Ensure that the bend angles associated with the differential signal pair are between 135o and 225o. (See Figure 9-14).
  • Minimize the length where the differential signal pair are parallel to clocks or digital signals.
  • Do not route the differential signal pair under an IC that uses a quartz crystal, oscillator, clock synchronization circuit, magnetic device, or clock.

GUID-720CCF29-4D1A-4CE1-BFE2-29BB681E2619-low.gifFigure 9-13 USB Layout Example
GUID-E70B5347-317D-41A8-813B-0E009B572158-low.gifFigure 9-14 USB Routing Example

Additional USB layout guidelines for TXRTUNE

  • Use the shortest possible connection lengths for the resistor between TXRTUNE and ground.
  • Use ground layer and ground guard traces to shield the wires and resistor.