ZHCSNH1C May   2021  – November 2022 DLPC6540

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  DMD HSSI Electrical Characteristics
    8. 6.8  DMD Low-Speed LVDS Electrical Characteristics
    9. 6.9  V-by-One Interface Electrical Characteristics
    10. 6.10 USB Electrical Characteristics
    11. 6.11 System Oscillator Timing Requirements
    12. 6.12 Power Supply and Reset Timing Requirements
    13. 6.13 DMD HSSI Timing Requirements
    14. 6.14 DMD Low-Speed LVDS Timing Requirements
    15. 6.15 V-by-One Interface General Timing Requirements
    16. 6.16 Source Frame Timing Requirements
    17. 6.17 Synchronous Serial Port Interface Timing Requirements
    18. 6.18 Master and Slave I2C Interface Timing Requirements
    19. 6.19 Programmable Output Clock Timing Requirements
    20. 6.20 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
    21. 6.21 JTAG ARM Multi-Ice Interface Timing Requirements (Debug Only)
    22. 6.22 Multi-Trace ETM Interface Timing Requirements
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Sources
      2. 7.3.2 Processing Delays
      3. 7.3.3 V-by-One Interface
      4. 7.3.4 DMD (HSSI) Interface
      5. 7.3.5 Program Memory Flash Interface
      6. 7.3.6 GPIO Supported Functionality
      7. 7.3.7 Debug Support
    4. 7.4 Device Operational Modes
      1. 7.4.1 Standby Mode
      2. 7.4.2 Active Mode
        1. 7.4.2.1 Normal Configuration
  8. Power Supply Recommendations
    1. 8.1 Power Supply Management
    2. 8.2 Hot Plug Usage
    3. 8.3 Power Supplies for Unused Input Source Interfaces
    4. 8.4 Power Supplies
      1. 8.4.1 1.15-V Power Supplies
      2. 8.4.2 1.21V Power Supply
      3. 8.4.3 1.8-V Power Supplies
      4. 8.4.4 3.3-V Power Supplies
  9. Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 General Layout Guidelines
      2. 9.1.2 Power Supply Layout Guidelines
      3. 9.1.3 Layout Guidelines for Internal Controller PLL Power
      4. 9.1.4 Layout Guideline for DLPC6540 Reference Clock
        1. 9.1.4.1 Recommended Crystal Oscillator Configuration
      5. 9.1.5 V-by-One Interface Layout Considerations
      6. 9.1.6 USB Interface Layout Considerations
      7. 9.1.7 DMD Interface Layout Considerations
      8. 9.1.8 General Handling Guidelines for Unused CMOS-Type Pins
      9. 9.1.9 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
    2. 9.2 Thermal Considerations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 第三方产品免责声明
      2. 10.1.2 Device Nomenclature
        1. 10.1.2.1 Device Markings
        2. 10.1.2.2 Package Data
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 术语表
      1. 10.6.1 Video Timing Parameter Definitions
  11. 11Mechanical, Packaging, and Orderable Information
    1.     79

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Maximum Pin-to-Pin, PCB Interconnects Etch Lengths

Table 9-8 Max Pin-to-Pin PCB Interconnect Recommendations - DMD
Controller INTERFACESIGNAL INTERCONNECT TOPOLOGY (1)(2)(3)UNIT
DMDSINGLE BOARD SIGNAL ROUTING LENGTHMULTI-BOARD SIGNAL ROUTING LENGTH
DMD_HSSI0_CLK_P
DMD_HSSI0_CLK_N
10 (254)Controller PCB: 2 (50.8)
DMD PCB: 4 (101.6)
Flex: 10 (254)
inch (mm)
DMD_HSSI0_D0_P
DMD_HSSI0_D0_N
10 (254)Controller PCB: 2 (50.8)
DMD PCB: 4 (101.6)
Flex: 10 (254)
inch (mm)
DMD_HSSI0_D1_P
DMD_HSSI0_D1_N
DMD_HSSI0_D2_P
DMD_HSSI0_D2_N
DMD_HSSI0_D3_P
DMD_HSSI0_D3_N
DMD_HSSI0_D4_P
DMD_HSSI0_D4_N
DMD_HSSI0_D5_P
DMD_HSSI0_D5_N
DMD_HSSI0_D6_P
DMD_HSSI0_D6_N
DMD_HSSI0_D7_P
DMD_HSSI0_D7_N
DMD_HSSI1_CLK_P
DMD_HSSI1_CLK_N
10 (254)Controller PCB: 2 (50.8)
DMD PCB: 4 (101.6)
Flex: 10 (254)
inch (mm)
DMD_HSSI1_D0_P
DMD_HSSI1_D0_N
10 (254)Controller PCB: 2 (50.8)
DMD PCB: 4 (101.6)
Flex: 10 (254)
inch (mm)
DMD_HSSI1_D1_P
DMD_HSSI1_D1_N
DMD_HSSI1_D2_P
DMD_HSSI1_D2_N
DMD_HSSI1_D3_P
DMD_HSSI1_D3_N
DMD_HSSI1_D4_P
DMD_HSSI1_D4_N
DMD_HSSI1_D5_P
DMD_HSSI1_D5_N
DMD_HSSI1_D6_P
DMD_HSSI1_D6_N
DMD_HSSI1_D7_P
DMD_HSSI1_D7_N
DMD_LS0_CLK_P
DMD_LS0_CLK_N
18
(457.2)
18
(457.2)
inch
(mm)
DMD_LS0_WDATA_P
DMD_LS0_WDATA_N
18
(457.2)
18
(457.2)
inch
(mm)
DMD_LS1_CLK_P
DMD_LS1_CLK_N
18
(457.2)
18
(457.2)
inch
(mm)
DMD_LS1_WDATA_P
DMD_LS1_WDATA_N
18
(457.2)
18
(457.2)
inch
(mm)
DMD_LS0_RDATA18
(457.2)
18
(457.2)
inch
(mm)
DMD_LS1_RDATA18
(457.2)
18
(457.2)
inch
(mm)
DMD_DEN_ARSTZN/AN/Ainch
(mm)
Max signal routing length includes escape routing.
Multi-board DMD routing lengths shown are the combination that was analyzed by TI.
Due to board variations, create a SPICE simulation for all board designs with the Controller IBIS models to ensure signal routing lengths do not exceed signal requirements.
Table 9-9 High Speed PCB Signal Routing Matching Requirements
SIGNAL GROUP LENGTH MATCHING (1)(2)
INTERFACESIGNAL GROUPREFERENCE SIGNALMAX MISMATCH (3)UNIT
DMD (4)DMD_HSSI0_D0_P
DMD_HSSI0_D0_N
DMD_HSSI0_CLK_P
DMD_HSSI0_CLK_N
±1.0
(±25.4)
inch
(mm)
DMD_HSSI0_D1_P
DMD_HSSI0_D1_N
DMD_HSSI0_D2_P
DMD_HSSI0_D2_N
DMD_HSSI0_D3_P
DMD_HSSI0_D3_N
DMD_HSSI0_D4_P
DMD_HSSI0_D4_N
DMD_HSSI0_D5_P
DMD_HSSI0_D5_N
DMD_HSSI0_D6_P
DMD_HSSI0_D6_N
DMD_HSSI0_D7_P
DMD_HSSI0_D7_N
DMD (5)DMD_HSSI0_x_PDMD_HSSI0_x_N±0.01
(±0.254)
inch
(mm)
DMD (4)DMD_HSSI1_D0_P
DMD_HSSI1_D0_N
DMD_HSSI1_CLK_P
DMD_HSSI1_CLK_N
±1.0
(±25.4)
inch
(mm)
DMD_HSSI1_D1_P
DMD_HSSI1_D1_N
DMD_HSSI1_D2_P
DMD_HSSI1_D2_N
DMD_HSSI1_D3_P
DMD_HSSI1_D3_N
DMD_HSSI1_D4_P
DMD_HSSI1_D4_N
DMD_HSSI1_D5_P
DMD_HSSI1_D5_N
DMD_HSSI1_D6_P
DMD_HSSI1_D6_N
DMD_HSSI1_D7_P
DMD_HSSI1_D7_N
DMD (5)DMD_HSSI1_x_PDMD_HSSI1_x_N±0.01
(±0.254)
inch
(mm)
DMD (6)DMD_HSSI0_CLK_PDMD_HSSI1_CLK_P±0.05
(±1.27)
inch
(mm)
DMD (6)DMD_HSSI0_CLK_NDMD_HSSI1_CLK_N±0.05
(±1.27)
inch
(mm)
DMD (4)DMD_LS0_WDATA_P
DMD_LS0_WDATA_N
DMD_LS0_CLK_P
DMD_LS0_CLK_N
±1.0
(±25.4)
inch
(mm)
DMD (5)DMD_LS0_x_PDMD_LS0_x_N±0.025
(±0.635)
inch
(mm)
DMD (4)DMD_LS1_WDATA_P
DMD_LS1_WDATA_N
DMD_LS1_CLK_P
DMD_LS1_CLK_N
±1.0
(±25.4)
inch
(mm)
DMD (5)DMD_LS1_x_PDMD_LS1_x_N±0.025
(±0.635)
inch
(mm)
DMDDMD_LS0_RDATA
DMD_LS1_RDATA
N/AN/A (7)inch
(mm)
DMDDMD_DEN_ARSTZN/AN/Ainch
(mm)
These routing requirements are specific to the PCB routing. Internal package routing mismatches in the DLPC6540 and DLP471TP have already been accounted for in these requirements.
Training is applied to DMD HS data lines, so defined matching requirements are slightly relaxed.
This requirement must be maintained from the Controller to the DMD, even if the signals traverse multiple boards.
This is an inter-pair specification (that is, differential pair to differential pair within the group).
This is an intra-pair specification (that is, length mismatch between P and N for the same pair). This is applicable to both clock and data.
This is a channel to channel skew specification.
The low speed read control interface from the DMD is single ended, and makes use of the differential write clock. As such, a routing mismatch between these is not applicable.