ZHCSNH1C May 2021 – November 2022 DLPC6540
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Power Electrical Characteristics
- 6.6 Pin Electrical Characteristics
- 6.7 DMD HSSI Electrical Characteristics
- 6.8 DMD Low-Speed LVDS Electrical Characteristics
- 6.9 V-by-One Interface Electrical Characteristics
- 6.10 USB Electrical Characteristics
- 6.11 System Oscillator Timing Requirements
- 6.12 Power Supply and Reset Timing Requirements
- 6.13 DMD HSSI Timing Requirements
- 6.14 DMD Low-Speed LVDS Timing Requirements
- 6.15 V-by-One Interface General Timing Requirements
- 6.16 Source Frame Timing Requirements
- 6.17 Synchronous Serial Port Interface Timing Requirements
- 6.18 Master and Slave I2C Interface Timing Requirements
- 6.19 Programmable Output Clock Timing Requirements
- 6.20 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
- 6.21 JTAG ARM Multi-Ice Interface Timing Requirements (Debug Only)
- 6.22 Multi-Trace ETM Interface Timing Requirements
- 7 Detailed Description
- 8 Power Supply Recommendations
-
9 Layout
- 9.1
Layout Guidelines
- 9.1.1 General Layout Guidelines
- 9.1.2 Power Supply Layout Guidelines
- 9.1.3 Layout Guidelines for Internal Controller PLL Power
- 9.1.4 Layout Guideline for DLPC6540 Reference Clock
- 9.1.5 V-by-One Interface Layout Considerations
- 9.1.6 USB Interface Layout Considerations
- 9.1.7 DMD Interface Layout Considerations
- 9.1.8 General Handling Guidelines for Unused CMOS-Type Pins
- 9.1.9 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
- 9.2 Thermal Considerations
- 9.1
Layout Guidelines
- 10Device and Documentation Support
- 11Mechanical, Packaging, and Orderable Information
6.11 System Oscillator Timing Requirements
| PARAMETER | MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|---|
| ƒclock | Clock frequency, REFCLKA(1)(2) | PLLA: 40 MHz | 39.9960 | 40.000 | 40.0040 | MHz |
| tc | Cycle time, REFCLKA(1) | PLLA: 40 MHz | 24.9975 | 25.000 | 25.0025 | ns |
| tw(H) | Pulse duration(3), REFCLKA, high | PLLA: 40 MHz 50% to 50% reference points (signal) | 11.25 | ns | ||
| tw(L) | Pulse duration(3), REFCLKA, low | PLLA: 40 MHz 50% to 50% reference points (signal) | 11.25 | ns | ||
| tt | Transition time(3), REFCLKA, tt = tƒ / tr | PLLA: 40 MHz 20% to 80% reference points (signal) | 2.5 | ns | ||
| tjp | Long term periodic jitter(3), REFCLKA (that is the deviation in period from ideal period due solely to high frequency jitter) | PLLA: 40 MHz | 18 | ps | ||
| fclock | Clock frequency, REFCLKB(1) | PLLB: 38 MHz | 37.9962 | 38.000 | 38.0038 | MHz |
| tc | Cycle time, REFCLKB(1) | PLLB: 38 MHz | 26.3132 | 26.3157 | 26.3184 | ns |
| tw(H) | Pulse duration(3), REFCLKB, high | PLLB: 38 MHz 50% to 50% reference points (signal) | 11.84 | ns | ||
| tw(L) | Pulse duration(3), REFCLKB, low | PLLB: 38 MHz 50% to 50% reference points (signal) | 11.84 | ns | ||
| tt | Transition time(3), REFCLKB, tt = tƒ / tr | PLLB: 38 MHz 20% to 80% reference points (signal) | 2.63 | ns | ||
| tjp | Long term periodic jitter(3), REFCLKB (that is the deviation in period from ideal period due solely to high frequency jitter) | PLLB: 38 MHz | 18 | ps | ||
(1) The REFCLK inputs do not support spread spectrum clock spreading.
(2) Multi-controller
systems require that a single oscillator be used to drive the REFCLKA input for
all controllers in the system.
(3) Applies only when driven through an external digital oscillator. This is a
1-sigma
RMS value.
Figure 6-4 System Oscillators