ZHCSNU9F april 2021 – january 2023 AM2431 , AM2432 , AM2434
PRODUCTION DATA
请参考 PDF 数据表获取器件具体的封装图。
Power is supplied to the Phase-Locked Loop circuits (PLLs) by internal regulators that derive their power from off-chip power-sources.
There is one PLL in the MCU domain:
There are six PLLs in the MAIN domain:
For more information, see:
The input reference clock (MCU_OSC0_XI / MCU_OSC0_XO) is specified and the lock time is ensured by the PLL controller, as documented in the Device Configuration chapter in the device TRM.