ZHCSJY1A June   2019  – January 2021 ADS125H01

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Timing Diagrams
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Performance
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Input Voltage Range
      2. 9.3.2 Analog Inputs (AINP, AINN)
        1. 9.3.2.1 ESD Diodes
        2. 9.3.2.2 Input Switch
      3. 9.3.3 Programmable Gain Amplifier (PGA)
        1. 9.3.3.1 PGA Operating Range
        2. 9.3.3.2 PGA Monitors
      4. 9.3.4 Reference Voltage
        1. 9.3.4.1 Reference Monitor
      5. 9.3.5 ADC Modulator
      6. 9.3.6 Digital Filter
        1. 9.3.6.1 Sinc Filter Mode
          1. 9.3.6.1.1 Sinc Filter Frequency Response
        2. 9.3.6.2 FIR Filter
        3. 9.3.6.3 50-Hz and 60-Hz Normal-Mode Rejection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Conversion Control
        1. 9.4.1.1 Continuous-Conversion Mode
        2. 9.4.1.2 Pulse-Conversion Mode
        3. 9.4.1.3 Conversion Latency
        4. 9.4.1.4 Start-Conversion Delay
      2. 9.4.2 Clock Mode
      3. 9.4.3 Reset
        1. 9.4.3.1 Power-On Reset
        2. 9.4.3.2 Reset by RESETPin
        3. 9.4.3.3 Reset by Command
      4. 9.4.4 Calibration
        1. 9.4.4.1 Offset and Full-Scale Calibration
          1. 9.4.4.1.1 Offset Calibration Registers
          2. 9.4.4.1.2 Full-Scale Calibration Registers
        2. 9.4.4.2 Offset Calibration Command (OFSCAL)
        3. 9.4.4.3 Full-Scale Calibration Command (GANCAL)
        4. 9.4.4.4 Calibration Command Procedure
        5. 9.4.4.5 User Calibration Procedure
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Chip-Select Pins (CS1 and CS2)
        2. 9.5.1.2 Serial Clock (SCLK)
        3. 9.5.1.3 Data Input (DIN)
        4. 9.5.1.4 Data Output/Data Ready (DOUT/DRDY)
      2. 9.5.2 Data Ready (DRDY)
        1. 9.5.2.1 DRDY in Continuous-Conversion Mode
        2. 9.5.2.2 DRDY in Pulse-Conversion Mode
        3. 9.5.2.3 Data Ready by Software Polling
      3. 9.5.3 Conversion Data
        1. 9.5.3.1 Status Byte (STATUS0)
        2. 9.5.3.2 Conversion Data Format
      4. 9.5.4 Cyclic Redundancy Check (CRC)
      5. 9.5.5 Commands
        1. 9.5.5.1  General Command Format
        2. 9.5.5.2  NOP Command
        3. 9.5.5.3  RESET Command
        4. 9.5.5.4  START Command
        5. 9.5.5.5  STOP Command
        6. 9.5.5.6  RDATA Command
        7. 9.5.5.7  OFSCAL Command
        8. 9.5.5.8  GANCAL Command
        9. 9.5.5.9  RREG Command
        10. 9.5.5.10 WREG Command
    6. 9.6 Register Map
      1. 9.6.1  Device Identification (ID) Register (address = 00h) [reset = 4xh]
      2. 9.6.2  Main Status (STATUS0) Register (address = 01h) [reset = 01h]
      3. 9.6.3  Mode 0 (MODE0) Register (address = 02h) [reset = 24h]
      4. 9.6.4  Mode 1 (MODE1) Register (address = 03h) [reset = 01h]
      5. 9.6.5  Reserved (RESERVED) Register (address = 04h) [reset = 00h]
      6. 9.6.6  Mode 3 (MODE3) Register (address = 05h) [reset = 00h]
      7. 9.6.7  Reference Configuration (REF) Register (address = 06h) [reset = 05h]
      8. 9.6.8  Offset Calibration (OFCALx) Registers (address = 07h, 08h, 09h) [reset = 00h, 00h, 00h]
      9. 9.6.9  Full-Scale Calibration (FSCALx) Registers (address = 0Ah, 0Bh, 0Ch) [reset = 00h, 00h, 40h]
      10. 9.6.10 Reserved (RESERVED) Register (address = 0Dh) [reset = FFh]
      11. 9.6.11 Reserved (RESERVED) Register (address = 0Eh) [reset = 00h]
      12. 9.6.12 Reserved (RESERVED) Register (address = 0Fh) [reset = 00h]
      13. 9.6.13 MODE4 (MODE4) Register (address = 10h) [reset = 50h]
      14. 9.6.14 PGA Alarm (STATUS1) Register (address = 11h) [reset = xxh]
      15. 9.6.15 Status 2 (STATUS2) Register (address = 12h) [reset = 0xh]
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Example to Determine the PGA Linear Operating Range
      2. 10.1.2 Input Signal Rate of Change (dV/dt)
      3. 10.1.3 Unused Inputs and Outputs
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Decoupling
    2. 11.2 Analog Power-Supply Clamp
    3. 11.3 Power-Supply Sequencing
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 接收文档更新通知
    3. 13.3 支持资源
    4. 13.4 Trademarks
    5. 13.5 静电放电警告
    6. 13.6 术语表
  14. 14Mechanical, Packaging, and Orderable Information

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7.5 Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all specifications are at HV_AVDD = 15 V, HV_AVSS = –15 V, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V, fCLK = 7.3728 MHz, data rate = 20 SPS, and gain = 1 (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
ANALOG INPUTS
Absolute input currentV(AINx) = 0 V, TA ≤ 105°C–15±0.515nA
Absolute input current drift20pA/°C
Differential input currentVIN = 2.5 V±0.1nA
Differential input current driftVIN = 2.5 V10pA/°C
Differential input impedance120GΩ
PGA
Gain settings0.125, 0.1875, 0.25, 0.5, 1, 2, 4, 8, 16, 32, 64,128V/V
Antialias filter frequency230kHz
PERFORMANCE
ResolutionNo missing codes24Bits
enNoise performanceSee the Section 8.1 section
fDATAData rate2.540000SPS
INLIntegral nonlinearityGain = 0.125 to 32210ppmFSR
Gain = 64, 128412
VOSOffset error(4)TA = 25°C–30 – 300 / Gain±10 + 100 / Gain30 + 300 / GainµV
Offset error driftGain = 0.125 to 8150 / Gain700 / GainnV/°C
Gain = 16 to 1281050
GEGain error(4)TA = 25°C, all gains–0.7%±0.1%0.7%
Gain driftAll gains14ppm/°C
NMRRNormal-mode rejection ratio(1)See the Section 9.3.6.3 section
CMRRCommon-mode rejection ratio(2)Data rate = 20 SPS130dB
Data rate = 400 SPS90105
PSRRPower-supply rejection ratio(3)HV_AVDD, HV_AVSS220µV/V
AVDD2060
DVDD530
VOLTAGE REFERENCE INPUTS
Absolute input current±250nA
Input current vs reference voltage15nA/V
Input current drift0.2nA/°C
Effective input impedanceDifferential30MΩ
PGA MONITORS
Input and output low thresholdHV_AVSS + 2V
Input and output high thresholdHV_AVDD – 2V
REFERENCE MONITOR
Low voltage threshold0.40.6V
INTERNAL OSCILLATOR
AccuracyfDATA ≤ 25.6 kSPS–2.5%±0.5%2.5%
fDATA = 40 kSPS–3.5%±0.5%3.5%
DIGITAL INPUTS/OUTPUTS
VOHHigh-level output voltageIOH = 1 mA0.8 × DVDDV
IOH = 8 mA0.75 × DVDD
VOLLow-level output voltageIOL = –1 mA0.2 × DVDDV
IOL = –8 mA0.2 × DVDD
VIHHigh-level input voltage0.7 × DVDDDVDDV
VILLow-level input voltage0.3 × DVDDV
Input hysteresis0.1V
Input leakage–1010µA
POWER SUPPLY
IHV_AVDD,
IHV_AVSS		HV_AVDD, HV_AVSS supply current1.11.8mA
IAVDDAVDD supply currentfDATA ≤ 25.6 kSPS2.84.6mA
fDATA = 40 kSPS3.6
IDVDDDVDD supply currentInternal oscillator active0.50.7mA
fDATA = 40 kSPS0.71
PDPower dissipation4979mW
(1) Normal-mode rejection ratio performance is dependent on the digital filter configuration.
(2) Common-mode rejection ratio is specified at fIN = 50 Hz and 60 Hz.
(3) Power-supply rejection ratio is specified at DC.
(4) Offset and gain errors are reduced to the level of noise by calibration.