ZHCSJY1A June 2019 – January 2021 ADS125H01
PRODUCTION DATA
Good layout practices are crucial to realize the full performance of the ADC. Poor grounding can quickly degrade the ADC noise performance. This section discusses layout recommendations that help provide the best results.
For best performance, dedicate an entire PCB layer to a ground plane and do not route any other signal traces on this layer. However, depending on layout restrictions, a dedicated ground plane may not be practical. If ground plane separation is necessary, make a single, direct connection to the planes at the ADC. Do not connect individual ground planes at multiple locations because this configuration creates ground loops.
Route digital signals away from the CAPP and CAPN pins and away from all analog inputs and associated components to prevent crosstalk.
Because large capacitance on DOUT/DRDY can lead to increased ADC noise levels, minimize the length of the PCB trace. Use a series resistor or a buffer if long traces are used.
Use C0G capacitors for the analog input filter and for the CAPP to CAPN capacitor. Use ceramic capacitors (for example, X7R grade) for the power-supply decoupling capacitors. High-K capacitors (Y5V) are not recommended. Place the required capacitors as close as possible to the device pins using short, direct traces. For optimum performance, use low-impedance connections with multiple vias on the ground-side connections of the bypass capacitors.
When applying an external clock, be sure the clock is free of overshoot and glitches. A source-termination resistor placed at the clock buffer often helps reduce overshoot. Glitches present on the clock input can lead to noisy conversion data.