SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
As an orthogonal axis to arbitration priority MSMC provides two classes of traffic, real-time (RT) and nonreal-time (NRT), to maintain quality-of-service (QoS) guarantees and alleviate head-of-line blocking issues. The currently implemented dataflows supported by the QoS hardware are:
At a high-level priority and QoS represent orthogonal axes controlling the latency (priority) and bandwidth protection (QoS) for multiple data flows routed through the MSMC. To accomplish this MSMC provides a dedicated buffering at each arbitration point that can only be consumed by RT traffic. This way NRT traffic cannot completely starve out RT requests.
The SoC coherent and external memory interfaces need dedicated credits to support QoS. Each of these interfaces implements additional threading to exchange these dedicated credits.
Thread Index | [0] | [2] |
---|---|---|
SoC Coherent Slave | CPU | RT_CPU |
External Memory Master | CPU | RT_CPU |
The RT_CPU thread provides a completely separate pool of credits, where necessary, to implement the dedicated buffers for RT traffic.
There is no software control over the MSMC QoS hardware.
Interfaces which do not support QoS features denote all traffic as nonreal-time.