SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Step | Register/Bit Field/Programming Model | Value |
---|---|---|
Power up the AFE | ADC_CONTROL[4] PD | 0 |
If using DMA, set the DMA threshold and enable the appropriate DMA request(s); or set the processor threshold and enable the appropriate threshold interrupt(s) as part of the next step. | ADC_DMAENABLE_SET/ADC_FIFO0DMAREQ/ ADC_FIFO1DMAREQ/ ADC_FIFO0THRESHOLD/ ADC_FIFO1THRESHOLD | 0x- |
Setup or mask the appropriate interrupts. | ADC_ENABLE_SET | 0x- |
Configure each step being used to perform an ADC conversion. | ADC_STEPCONFIG_j | 0x- |
Configure the delays for each step being used to perform an ADC conversion. | ADC_STEPDELAY_j | 0x- |
Enable each step being used to perform an ADC conversion. | ADC_STEPENABLE | 0x- |
Wait minimum 4 µs before starting a conversion to provide time for the AFE to power-up. (referenced from POWER_DOWN write to 0) | ||
Enable the ADC module | ADC_CONTROL[0] MODULE_ENABLE | 1 |