The ECC calculation is generated or checked on the concatenated structure {BIT('1'),BLOCK_ADDRESS[26-0],WORD1[127-0],WORD0[127-0]} broken into four 71-bit chunks stored in the ECC word. The ECC word has four 8-bits values. Each value checks a 71-bit segment of the concatenated structure.
Details:
- The 71-bit portion uses a standard 7-bit ECC calculation plus a parity bit (8-bit value).
- The WORD0[127-0] is the first 128-bit word of a block and the WORD1[127-0] is the second 128-bit word of the data block.
- The BLOCK_ADDRESS[26-0] is the upper 27 bits of the requested byte address known as the block address.
- If the MCU_FSS0_SYSCONFIG[3] ECC_DISABLE_ADR bit
is set, the BLOCK_ADDRESS[26-0] is assumed zero so that it does not affect the
ECC calculation.
- If the ECC detects a double error, the returned data is cleared to zero.
- Both SEC and DED are reported to the ECC registers.
For more information about ECC registers, see
FSS Registers.