SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
A single DDRSS0 module is integrated in the device MAIN domain. Figure 8-41 shows the integration of DDRSS0.
Table 8-82 through Table 8-84 summarize the integration of DDRSS0 in device MAIN domain.
Module Instance | Attributes | ||||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | ||
DDRSS0 | PSC0 | PD0 | LPSC15 | CBASS0 (Accessed through MSMC) |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
DDRSS0 | DDRSS0_ICLK | MAIN_SYSCLK0/2 | PLLCTRL0 | DDRSS0 configuration interface clock |
DDRSS0_FCLK | MAIN_PLL12_HSDIV0_CLKOUT | PLL12 | DDRSS0 functional clock. It supplies the SDRAM clock. | |
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
DDRSS0 | DDRSS0_RST | MOD_G_RST | LPSC15 | DDRSS0 reset |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
DDRSS0 | DDR0_DDRSS_CONTROLLER_GLOBAL_ERROR_NONFATAL_0 | ESM0_LVL_IN_32 | ESM0 | DDR controller interrupt associated with bit [0] of the DDRSS_CTL_437[31-24] GLOBAL_ERROR_INFO field | Level |
DDR0_DDRSS_CONTROLLER_GLOBAL_ERROR_FATAL_0 | ESM0_LVL_IN_33 | ESM0 | DDR controller interrupt associated with bits [7-1] of the DDRSS_CTL_437[31-24] GLOBAL_ERROR_INFO field | Level | |
DDR0_DDRSS_CFG_ECC_AGGR_CORR_ERR_LVL_0 | ESM0_LVL_IN_292 | ESM0 | DDRSS0_ECC_AGGR_CFG correctable error interrupt | Level | |
DDR0_DDRSS_CFG_ECC_AGGR_UNCORR_ERR_LVL_0 | ESM0_LVL_IN_293 | ESM0 | DDRSS0_ECC_AGGR_CFG non-correctable error interrupt | Level | |
DDR0_DDRSS_CTL_ECC_AGGR_CORR_ERR_LVL_0 | ESM0_LVL_IN_294 | ESM0 | DDRSS0_ECC_AGGR_CTL correctable error interrupt | Level | |
DDR0_DDRSS_CTL_ECC_AGGR_UNCORR_ERR_LVL_0 | ESM0_LVL_IN_295 | ESM0 | DDRSS0_ECC_AGGR_CTL non-correctable error interrupt | Level | |
DDR0_DDRSS_VBUS_ECC_AGGR_CORR_ERR_LVL_0 | ESM0_LVL_IN_296 | ESM0 | DDRSS0_ECC_AGGR_VBUS correctable error interrupt | Level | |
DDR0_DDRSS_VBUS_ECC_AGGR_UNCORR_ERR_LVL_0 | ESM0_LVL_IN_297 | ESM0 | DDRSS0_ECC_AGGR_VBUS non-correctable error interrupt | Level | |
DDR0_DDRSS_DRAM_ECC_CORR_ERR_LVL_0 | ESM0_LVL_IN_298 | ESM0 | MSMC2DDR bridge 1-bit error interrupt. See Section 8.2.4.1.4.2. | Level | |
DDR0_DDRSS_DRAM_ECC_UNCORR_ERR_LVL_0 | ESM0_LVL_IN_299 | ESM0 | MSMC2DDR bridge 2-bit error interrupt. See Section 8.2.4.1.4.2. | Level | |
DDR0_DDRSS_CONTROLLER_0 | GIC500_SPI_IN_248 | GIC500 | DDR controller common interrupt | Level | |
R5FSS0_CORE0_INTR_IN_313 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_313 | R5FSS0_CORE1 | ||||
MAIN2MCU_LVL_INTRTR0_IN_10 | MAIN2MCU_LVL_INTRTR0 | ||||
DDR0_DDRSS_V2A_OTHER_ERR_LVL_0 | GIC500_SPI_IN_249 | GIC500 | MSMC2DDR bridge interrupt indicating:
| Level | |
R5FSS0_CORE0_INTR_IN_314 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_314 | R5FSS0_CORE1 | ||||
MAIN2MCU_LVL_INTRTR0_IN_11 | MAIN2MCU_LVL_INTRTR0 | ||||
DDR0_DDRSS_HS_PHY_GLOBAL_ERROR_0 | GIC500_SPI_IN_250 | GIC500 | DDR PHY global error interrupt | Level | |
ESM0_LVL_IN_34 | ESM0 | ||||
R5FSS0_CORE0_INTR_IN_315 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_315 | R5FSS0_CORE1 | ||||
MAIN2MCU_LVL_INTRTR0_IN_12 | MAIN2MCU_LVL_INTRTR0 | ||||
DDR0_DDRSS_PLL_FREQ_CHANGE_REQ_0 | GIC500_SPI_IN_251 | GIC500 | DDRSS0 frequency change request interrupt. See Section 8.2.4.5. | Level | |
R5FSS0_CORE0_INTR_IN_316 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_316 | R5FSS0_CORE1 | ||||
MAIN2MCU_LVL_INTRTR0_IN_9 | MAIN2MCU_LVL_INTRTR0 | ||||
DMA Events | |||||
Module Instance | Module DMA Event | Destination DMA Event Input | Destination | Description | Type |
DDRSS0 | - | - | - | - | - |
For more information about the DDRSS0 interrupts, see Section 8.2.4.2.
For more information on the interconnects, see Chapter 3, System Interconnect.
For more information on the power, reset and clock management, see the corresponding sections within Chapter 5, Device Configuration.
For more information on the device interrupt controllers, see Section 9.2, Interrupt Controllers.