SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
A single I3C0 module is integrated in the device MAIN domain. Figure 12-176 shows the integration of I3C0.
Table 12-328 through Table 12-330 summarize the integration of I3C0 in the device MAIN domain.
Module Instance | Attributes | |||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | |
I3C0 | PSC0 | PD0 | LPSC33 | CBASS0 |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
I3C0 | I3C0_PCLK | MAIN_SYSCLK0/4 | PLLCTRL0 | I3C0 configuration clock |
I3C0_SCLK | I3C0 system clock | |||
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
I3C0 | I3C0_RST | MOD_G_RST | LPSC33 | I3C0 reset |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
I3C0 | I3C0_I3C_INT_0 | GIC500_SPI_IN_284 | COMPUTE_CLUSTER0 | I3C0 interrupt request | Level |
R5FSS0_CORE0_INTR_IN_274 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_274 | R5FSS0_CORE1 | ||||
MAIN2MCU_LVL_INTRTR0_IN_220 | MAIN2MCU_LVL_INTRTR0 | ||||
I3C0_PCLK_ECC_UNCORR_LVL_0 | ESM0_LVL_IN_152 | ESM0 | I3C0 PCLK ECC interrupt request | Level | |
I3C0_SCLK_ECC_UNCORR_LVL_0 | ESM0_LVL_IN_153 | I3C0 SCLK ECC interrupt request | Level | ||
I3C0_I3C_NONFATAL_INT_0 | ESM0_LVL_IN_154 | I3C0 non fatal interrupt request | Level | ||
I3C0_I3C_FATAL_INT_0 | ESM0_LVL_IN_155 | I3C0 fatal interrupt request | Level |