SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 10-141 lists the memory-mapped registers for the MCU_NAVSS0_UDMASS_ECCAGGR0 . All register offset addresses not listed in Table 10-141 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
MCU_NAVSS0_UDMASS_ECCAGGR0 | 2838 1000h |
Offset | Acronym | Register Name | MCU_NAVSS0_UDMASS_ECCAGGR0 Physical Address |
---|---|---|---|
0h | MCU_NAVSS_REV | Aggregator Revision Register | 2838 1000h |
8h | MCU_NAVSS_VECTOR | ECC Vector Register | 2838 1008h |
Ch | MCU_NAVSS_STAT | Misc Status | 2838 100Ch |
3Ch | MCU_NAVSS_SEC_EOI_REG | EOI Register | 2838 103Ch |
40h | MCU_NAVSS_SEC_STATUS_REG0 | Interrupt Status Register 0 | 2838 1040h |
44h | MCU_NAVSS_SEC_STATUS_REG1 | Interrupt Status Register 1 | 2838 1044h |
48h | MCU_NAVSS_SEC_STATUS_REG2 | Interrupt Status Register 2 | 2838 1048h |
4Ch | MCU_NAVSS_SEC_STATUS_REG3 | Interrupt Status Register 3 | 2838 104Ch |
80h | MCU_NAVSS_SEC_ENABLE_SET_REG0 | Interrupt Enable Set Register 0 | 2838 1080h |
84h | MCU_NAVSS_SEC_ENABLE_SET_REG1 | Interrupt Enable Set Register 1 | 2838 1084h |
88h | MCU_NAVSS_SEC_ENABLE_SET_REG2 | Interrupt Enable Set Register 2 | 2838 1088h |
8Ch | MCU_NAVSS_SEC_ENABLE_SET_REG3 | Interrupt Enable Set Register 3 | 2838 108Ch |
C0h | MCU_NAVSS_SEC_ENABLE_CLR_REG0 | Interrupt Enable Clear Register 0 | 2838 10C0h |
C4h | MCU_NAVSS_SEC_ENABLE_CLR_REG1 | Interrupt Enable Clear Register 1 | 2838 10C4h |
C8h | MCU_NAVSS_SEC_ENABLE_CLR_REG2 | Interrupt Enable Clear Register 2 | 2838 10C8h |
CCh | MCU_NAVSS_SEC_ENABLE_CLR_REG3 | Interrupt Enable Clear Register 3 | 2838 10CCh |
13Ch | MCU_NAVSS_DED_EOI_REG | EOI Register | 2838 113Ch |
140h | MCU_NAVSS_DED_STATUS_REG0 | Interrupt Status Register 0 | 2838 1140h |
144h | MCU_NAVSS_DED_STATUS_REG1 | Interrupt Status Register 1 | 2838 1144h |
148h | MCU_NAVSS_DED_STATUS_REG2 | Interrupt Status Register 2 | 2838 1148h |
14Ch | MCU_NAVSS_DED_STATUS_REG3 | Interrupt Status Register 3 | 2838 114Ch |
180h | MCU_NAVSS_DED_ENABLE_SET_REG0 | Interrupt Enable Set Register 0 | 2838 1180h |
184h | MCU_NAVSS_DED_ENABLE_SET_REG1 | Interrupt Enable Set Register 1 | 2838 1184h |
188h | MCU_NAVSS_DED_ENABLE_SET_REG2 | Interrupt Enable Set Register 2 | 2838 1188h |
18Ch | MCU_NAVSS_DED_ENABLE_SET_REG3 | Interrupt Enable Set Register 3 | 2838 118Ch |
1C0h | MCU_NAVSS_DED_ENABLE_CLR_REG0 | Interrupt Enable Clear Register 0 | 2838 11C0h |
1C4h | MCU_NAVSS_DED_ENABLE_CLR_REG1 | Interrupt Enable Clear Register 1 | 2838 11C4h |
1C8h | MCU_NAVSS_DED_ENABLE_CLR_REG2 | Interrupt Enable Clear Register 2 | 2838 11C8h |
1CCh | MCU_NAVSS_DED_ENABLE_CLR_REG3 | Interrupt Enable Clear Register 3 | 2838 11CCh |
200h | MCU_NAVSS_AGGR_ENABLE_SET | AGGR interrupt enable set Register | 2838 1200h |
204h | MCU_NAVSS_AGGR_ENABLE_CLR | AGGR interrupt enable clear Register | 2838 1204h |
208h | MCU_NAVSS_AGGR_STATUS_SET | AGGR interrupt status set Register | 2838 1208h |
20Ch | MCU_NAVSS_AGGR_STATUS_CLR | AGGR interrupt status clear Register | 2838 120Ch |
MCU_NAVSS_REV is shown in Figure 10-27 and described in Table 10-143.
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Revision parameters
Instance | Physical Address |
---|---|
MCU_NAVSS0_UDMASS_ECCAGGR0 | 2838 1000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | MODULE_ID | |||||||||||||
R-1h | R-2h | R-6A0h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVRTL | REVMAJ | CUSTOM | REVMIN | ||||||||||||
R-1Ch | R-2h | R-0h | R-0h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h | Scheme |
29-28 | BU | R | 2h | bu |
27-16 | MODULE_ID | R | 6A0h | Module ID |
15-11 | REVRTL | R | 1Ch | RTL version |
10-8 | REVMAJ | R | 2h | Major version |
7-6 | CUSTOM | R | 0h | Custom version |
5-0 | REVMIN | R | 0h | Minor version |
MCU_NAVSS_VECTOR is shown in Figure 10-28 and described in Table 10-145.
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ECC Vector Register
Instance | Physical Address |
---|---|
MCU_NAVSS0_UDMASS_ECCAGGR0 | 2838 1008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RD_SVBUS_DONE | ||||||
R/W-X | R/W1C-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RD_SVBUS_ADDRESS | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RD_SVBUS | RESERVED | ECC_VECTOR | |||||
R/W1S-0h | R/W-X | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC_VECTOR | |||||||
R/W-0h | |||||||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R/W | X | |
24 | RD_SVBUS_DONE | R/W1C | 0h | Status to indicate if read on serial VBUS is complete, write of any value will clear this bit. |
23-16 | RD_SVBUS_ADDRESS | R/W | 0h | Read address |
15 | RD_SVBUS | R/W1S | 0h | Write 1 to trigger a read on the serial VBUS |
14-11 | RESERVED | R/W | X | |
10-0 | ECC_VECTOR | R/W | 0h | Value written to select the corresponding ECC RAM for control or status |
MCU_NAVSS_STAT is shown in Figure 10-29 and described in Table 10-147.
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Misc Status
Instance | Physical Address |
---|---|
MCU_NAVSS0_UDMASS_ECCAGGR0 | 2838 100Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUM_RAMS | ||||||||||||||||||||||||||||||
R-X | R-78h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | X | |
10-0 | NUM_RAMS | R | 78h | Indicates the number of RAMS serviced by the ECC aggregator |
MCU_NAVSS_SEC_EOI_REG is shown in Figure 10-30 and described in Table 10-149.
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EOI Register
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
MCU_NAVSS0_UDMASS_ECCAGGR0 | 2838 103Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R/W-X | R/W1S-0h | ||||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | EOI_WR | R/W1S | 0h | EOI Register |
MCU_NAVSS_SEC_STATUS_REG0 is shown in Figure 10-31 and described in Table 10-151.
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Interrupt Status Register 0
Instance | Physical Address |
---|---|
MCU_NAVSS0_UDMASS_ECCAGGR0 | 2838 1040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
UDMAP0_RPCF1_RAMECC_PEND | UDMAP0_RPCF0_RAMECC_PEND | UDMAP0_RFFW_RAMECC_PEND | UDMAP0_TPCF4_RAMECC_PEND | UDMAP0_TPCF1_RAMECC_PEND | UDMAP0_TPCF0_RAMECC_PEND | UDMAP0_TSTATE_RAMECC_PEND | UDMAP0_RPCU_CNTR_RAMECC_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
UDMAP0_RPCU_SB1_RAMECC_PEND | UDMAP0_RPCU_SB0_RAMECC_PEND | UDMAP0_RPTRCU_CNTR_RAMECC_PEND | UDMAP0_RPTRSB2_RAMECC_PEND | UDMAP0_RPTRSB1_RAMECC_PEND | UDMAP0_RPTRSB0_RAMECC_PEND | UDMAP0_TPTRCU_CNTR_RAMECC_PEND | UDMAP0_TPTRSB2_RAMECC_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
UDMAP0_TPTRSB1_RAMECC_PEND | UDMAP0_TPTRSB0_RAMECC_PEND | UDMAP0_RPBUF_PF_RAMECC_PEND | UDMAP0_RPBUF_DF_RAMECC_PEND | UDMAP0_RPBUF_CF_RAMECC_PEND | UDMAP0_RPRQ_RAMECC_PEND | UDMAP0_RPCFG_RAMECC_PEND | UDMAP0_RPSTATE_RAMECC_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UDMAP0_TPCU_CNTR_RAMECC_PEND | UDMAP0_TPCU_RAMECC_PEND | UDMAP0_TPBUF_PF_RAMECC_PEND | UDMAP0_TPBUF_DF_RAMECC_PEND | UDMAP0_TPBUF_CF_RAMECC_PEND | UDMAP0_TPCFG_RAMECC_PEND | UDMAP0_TPSTATE_RAMECC_PEND | ECCAGG_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | UDMAP0_RPCF1_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rpcf1_ramecc_pend |
30 | UDMAP0_RPCF0_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rpcf0_ramecc_pend |
29 | UDMAP0_RFFW_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rffw_ramecc_pend |
28 | UDMAP0_TPCF4_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_tpcf4_ramecc_pend |
27 | UDMAP0_TPCF1_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_tpcf1_ramecc_pend |
26 | UDMAP0_TPCF0_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_tpcf0_ramecc_pend |
25 | UDMAP0_TSTATE_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_tstate_ramecc_pend |
24 | UDMAP0_RPCU_CNTR_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rpcu_cntr_ramecc_pend |
23 | UDMAP0_RPCU_SB1_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rpcu_sb1_ramecc_pend |
22 | UDMAP0_RPCU_SB0_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rpcu_sb0_ramecc_pend |
21 | UDMAP0_RPTRCU_CNTR_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rptrcu_cntr_ramecc_pend |
20 | UDMAP0_RPTRSB2_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rptrsb2_ramecc_pend |
19 | UDMAP0_RPTRSB1_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rptrsb1_ramecc_pend |
18 | UDMAP0_RPTRSB0_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rptrsb0_ramecc_pend |
17 | UDMAP0_TPTRCU_CNTR_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_tptrcu_cntr_ramecc_pend |
16 | UDMAP0_TPTRSB2_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_tptrsb2_ramecc_pend |
15 | UDMAP0_TPTRSB1_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_tptrsb1_ramecc_pend |
14 | UDMAP0_TPTRSB0_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_tptrsb0_ramecc_pend |
13 | UDMAP0_RPBUF_PF_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rpbuf_pf_ramecc_pend |
12 | UDMAP0_RPBUF_DF_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rpbuf_df_ramecc_pend |
11 | UDMAP0_RPBUF_CF_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rpbuf_cf_ramecc_pend |
10 | UDMAP0_RPRQ_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rprq_ramecc_pend |
9 | UDMAP0_RPCFG_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rpcfg_ramecc_pend |
8 | UDMAP0_RPSTATE_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rpstate_ramecc_pend |
7 | UDMAP0_TPCU_CNTR_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_tpcu_cntr_ramecc_pend |
6 | UDMAP0_TPCU_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_tpcu_ramecc_pend |
5 | UDMAP0_TPBUF_PF_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_tpbuf_pf_ramecc_pend |
4 | UDMAP0_TPBUF_DF_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_tpbuf_df_ramecc_pend |
3 | UDMAP0_TPBUF_CF_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_tpbuf_cf_ramecc_pend |
2 | UDMAP0_TPCFG_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_tpcfg_ramecc_pend |
1 | UDMAP0_TPSTATE_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_tpstate_ramecc_pend |
0 | ECCAGG_PEND | R/W1S | 0h | Interrupt Pending Status for eccagg_pend |
MCU_NAVSS_SEC_STATUS_REG1 is shown in Figure 10-32 and described in Table 10-153.
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Interrupt Status Register 1
Instance | Physical Address |
---|---|
MCU_NAVSS0_UDMASS_ECCAGGR0 | 2838 1044h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
UDMASS_INTA0_SR_ECC_PEND | UDMASS_INTA0_IM_ECC_PEND | NAVSS_MCU_UDMASS_UDMASS_INTA0_EDC_CTRL_BUSECC_PEND | RINGACC0_ECC_PEND | NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_1_PEND | NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_0_PEND | NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_2_PEND | NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_1_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_0_PEND | UDMAP0_RRNGOCC_RAMECC_PEND | UDMAP0_TRNGOCC_RAMECC_PEND | UDMAP0_PSILTID_RAMECC_PEND | UDMAP0_PSILR_RAMECC_PEND | UDMAP0_SDEC3_RAMECC_PEND | UDMAP0_SDEC0_RAMECC_PEND | UDMAP0_RDEC2_RAMECC_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
UDMAP0_RDEC1_RAMECC_PEND | UDMAP0_RDEC0_RAMECC_PEND | UDMAP0_REVTCNTR_RAMECC_PEND | UDMAP0_TEVTCNTR_RAMECC_PEND | UDMAP0_STS_RAMECC3_PEND | UDMAP0_STS_RAMECC2_PEND | UDMAP0_STS_RAMECC1_PEND | UDMAP0_STS_RAMECC0_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UDMAP0_EH_RAMECC_PEND | UDMAP0_PROXY_RAMECC_PEND | UDMAP0_RSTATE_RAMECC_PEND | UDMAP0_RFLOW1_RAMECC_PEND | UDMAP0_RFLOW0_RAMECC_PEND | UDMAP0_RPCF4_RAMECC_PEND | UDMAP0_RPCF3_RAMECC_PEND | UDMAP0_RPCF2_RAMECC_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | UDMASS_INTA0_SR_ECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmass_inta0_sr_ecc_pend |
30 | UDMASS_INTA0_IM_ECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmass_inta0_im_ecc_pend |
29 | NAVSS_MCU_UDMASS_UDMASS_INTA0_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_udmass_inta0_edc_ctrl_busecc_pend |
28 | RINGACC0_ECC_PEND | R/W1S | 0h | Interrupt Pending Status for ringacc0_ecc_pend |
27 | NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_1_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_1_pend |
26 | NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_0_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_0_pend |
25 | NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_2_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_udmap0_edc_ctrl_busecc_2_pend |
24 | NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_1_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_udmap0_edc_ctrl_busecc_1_pend |
23 | NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_0_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_udmap0_edc_ctrl_busecc_0_pend |
22 | UDMAP0_RRNGOCC_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rrngocc_ramecc_pend |
21 | UDMAP0_TRNGOCC_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_trngocc_ramecc_pend |
20 | UDMAP0_PSILTID_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_psiltid_ramecc_pend |
19 | UDMAP0_PSILR_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_psilr_ramecc_pend |
18 | UDMAP0_SDEC3_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_sdec3_ramecc_pend |
17 | UDMAP0_SDEC0_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_sdec0_ramecc_pend |
16 | UDMAP0_RDEC2_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rdec2_ramecc_pend |
15 | UDMAP0_RDEC1_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rdec1_ramecc_pend |
14 | UDMAP0_RDEC0_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rdec0_ramecc_pend |
13 | UDMAP0_REVTCNTR_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_revtcntr_ramecc_pend |
12 | UDMAP0_TEVTCNTR_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_tevtcntr_ramecc_pend |
11 | UDMAP0_STS_RAMECC3_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_sts_ramecc3_pend |
10 | UDMAP0_STS_RAMECC2_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_sts_ramecc2_pend |
9 | UDMAP0_STS_RAMECC1_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_sts_ramecc1_pend |
8 | UDMAP0_STS_RAMECC0_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_sts_ramecc0_pend |
7 | UDMAP0_EH_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_eh_ramecc_pend |
6 | UDMAP0_PROXY_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_proxy_ramecc_pend |
5 | UDMAP0_RSTATE_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rstate_ramecc_pend |
4 | UDMAP0_RFLOW1_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rflow1_ramecc_pend |
3 | UDMAP0_RFLOW0_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rflow0_ramecc_pend |
2 | UDMAP0_RPCF4_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rpcf4_ramecc_pend |
1 | UDMAP0_RPCF3_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rpcf3_ramecc_pend |
0 | UDMAP0_RPCF2_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rpcf2_ramecc_pend |
MCU_NAVSS_SEC_STATUS_REG2 is shown in Figure 10-33 and described in Table 10-155.
Return to Summary Table.
Interrupt Status Register 2
Instance | Physical Address |
---|---|
MCU_NAVSS0_UDMASS_ECCAGGR0 | 2838 1048h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_DST_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_SRC_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_DST_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_SRC_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_DST_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_SRC_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_DST_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_SRC_BUSECC_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NAVSS_MCU_UDMASS_PSILSS0_CFG_NAVSS_MCU_UDMASS_PSILSS0_CFG_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_BUSECC_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_EDC_CTRL_BUSECC_PEND | UDMASS_INTA0_GC_ECC_PEND | UDMASS_INTA0_MC_ECC_PEND | UDMASS_INTA0_LC_ECC_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_DST_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_pdma_mcu1_psil_d_data_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_data_bridge_dst_busecc_pend |
30 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_SRC_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_pdma_mcu1_psil_d_data_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_data_bridge_src_busecc_pend |
29 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_DST_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_cpsw0_psil_d_data_p2p_bridge_safeg_rt_cpsw0_psil_d_data_bridge_dst_busecc_pend |
28 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_SRC_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_cpsw0_psil_d_data_p2p_bridge_safeg_rt_cpsw0_psil_d_data_bridge_src_busecc_pend |
27 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_DST_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_pdma_mcu1_psil_s_data_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_data_bridge_dst_busecc_pend |
26 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_SRC_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_pdma_mcu1_psil_s_data_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_data_bridge_src_busecc_pend |
25 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_DST_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_cpsw0_psil_s_data_p2p_bridge_safeg_rt_cpsw0_psil_s_data_bridge_dst_busecc_pend |
24 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_SRC_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_cpsw0_psil_s_data_p2p_bridge_safeg_rt_cpsw0_psil_s_data_bridge_src_busecc_pend |
23 | NAVSS_MCU_UDMASS_PSILSS0_CFG_NAVSS_MCU_UDMASS_PSILSS0_CFG_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cfg_navss_mcu_udmass_psilss0_cfg_edc_ctrl_busecc_pend |
22 | NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_psilcfg0_cfgstrm_navss_mcu_udmass_psilss0_l2p_psilcfg0_cfgstrm_edc_ctrl_busecc_pend |
21 | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_udmap0_cfgstrm_navss_mcu_udmass_psilss0_l2p_udmap0_cfgstrm_edc_ctrl_busecc_pend |
20 | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_udmass_inta0_mevt_in_navss_mcu_udmass_psilss0_l2p_udmass_inta0_mevt_in_edc_ctrl_busecc_pend |
19 | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_udmass_inta0_cevt_navss_mcu_udmass_psilss0_l2p_udmass_inta0_cevt_edc_ctrl_busecc_pend |
18 | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_udmass_inta0_evt_navss_mcu_udmass_psilss0_l2p_udmass_inta0_evt_edc_ctrl_busecc_pend |
17 | NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_dmsc_evt_navss_mcu_udmass_psilss0_l2p_dmsc_evt_edc_ctrl_busecc_pend |
16 | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_udmap0_strm_navss_mcu_udmass_psilss0_l2p_udmap0_strm_edc_ctrl_busecc_pend |
15 | NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_pdma_mcu1_psil_navss_mcu_udmass_psilss0_l2p_pdma_mcu1_psil_edc_ctrl_busecc_pend |
14 | NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_pdma_mcu0_psil_navss_mcu_udmass_psilss0_l2p_pdma_mcu0_psil_edc_ctrl_busecc_pend |
13 | NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_cpsw0_psil_navss_mcu_udmass_psilss0_l2p_cpsw0_psil_edc_ctrl_busecc_pend |
12 | NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_navss_psil_navss_mcu_udmass_psilss0_l2p_navss_psil_edc_ctrl_busecc_pend |
11 | NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_psilcfg0_cfgstrm_bridge_navss_mcu_udmass_psilss0_psilcfg0_cfgstrm_bridge_edc_ctrl_busecc_pend |
10 | NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_udmap0_cfgstrm_bridge_navss_mcu_udmass_psilss0_udmap0_cfgstrm_bridge_edc_ctrl_busecc_pend |
9 | NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_psilcfg0_cfgstrm_safeg_navss_mcu_udmass_psilss0_psilcfg0_cfgstrm_safeg_edc_ctrl_busecc_pend |
8 | NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_udmap0_cfgstrm_safeg_navss_mcu_udmass_psilss0_udmap0_cfgstrm_safeg_edc_ctrl_busecc_pend |
7 | NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_udmap0_strm_safeg_navss_mcu_udmass_psilss0_udmap0_strm_safeg_edc_ctrl_busecc_pend |
6 | NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_pdma_mcu1_psil_safeg_navss_mcu_udmass_psilss0_pdma_mcu1_psil_safeg_edc_ctrl_busecc_pend |
5 | NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_pdma_mcu0_psil_safeg_navss_mcu_udmass_psilss0_pdma_mcu0_psil_safeg_edc_ctrl_busecc_pend |
4 | NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cpsw0_psil_safeg_navss_mcu_udmass_psilss0_cpsw0_psil_safeg_edc_ctrl_busecc_pend |
3 | NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_navss_psil_rt_bridge_navss_mcu_udmass_psilss0_navss_psil_rt_bridge_edc_ctrl_busecc_pend |
2 | UDMASS_INTA0_GC_ECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmass_inta0_gc_ecc_pend |
1 | UDMASS_INTA0_MC_ECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmass_inta0_mc_ecc_pend |
0 | UDMASS_INTA0_LC_ECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmass_inta0_lc_ecc_pend |
MCU_NAVSS_SEC_STATUS_REG3 is shown in Figure 10-34 and described in Table 10-157.
Return to Summary Table.
Interrupt Status Register 3
Instance | Physical Address |
---|---|
MCU_NAVSS0_UDMASS_ECCAGGR0 | 2838 104Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_4_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_3_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_2_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_1_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_0_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_D_DEF_EVT_BRIDGE_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_DST_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_SRC_BUSECC_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_DST_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_SRC_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_2_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_1_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_0_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_DST_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_SRC_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_DST_BUSECC_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_SRC_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_DST_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_SRC_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_DST_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_SRC_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_2_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_1_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_0_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R/W | X | |
23 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_4_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_edc_ctrl_busecc_4_pend |
22 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_3_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_edc_ctrl_busecc_3_pend |
21 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_2_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_edc_ctrl_busecc_2_pend |
20 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_1_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_edc_ctrl_busecc_1_pend |
19 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_0_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_edc_ctrl_busecc_0_pend |
18 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_D_DEF_EVT_BRIDGE_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_d_def_evt_p2p_bridge_d_def_evt_bridge_busecc_pend |
17 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_DST_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_safeg_rt_pdma_mcu1_psil_d_etl0_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_etl0_bridge_dst_busecc_pend |
16 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_SRC_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_safeg_rt_pdma_mcu1_psil_d_etl0_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_etl0_bridge_src_busecc_pend |
15 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_DST_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_safeg_rt_pdma_mcu1_psil_s_etl0_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_etl0_bridge_dst_busecc_pend |
14 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_SRC_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_safeg_rt_pdma_mcu1_psil_s_etl0_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_etl0_bridge_src_busecc_pend |
13 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_2_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_edc_ctrl_busecc_2_pend |
12 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_1_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_edc_ctrl_busecc_1_pend |
11 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_0_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_edc_ctrl_busecc_0_pend |
10 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_DST_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_pdma_mcu1_psil_s_resp_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_resp_bridge_dst_busecc_pend |
9 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_SRC_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_pdma_mcu1_psil_s_resp_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_resp_bridge_src_busecc_pend |
8 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_DST_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_cpsw0_psil_s_resp_p2p_bridge_safeg_rt_cpsw0_psil_s_resp_bridge_dst_busecc_pend |
7 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_SRC_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_cpsw0_psil_s_resp_p2p_bridge_safeg_rt_cpsw0_psil_s_resp_bridge_src_busecc_pend |
6 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_DST_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_pdma_mcu1_psil_d_resp_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_resp_bridge_dst_busecc_pend |
5 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_SRC_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_pdma_mcu1_psil_d_resp_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_resp_bridge_src_busecc_pend |
4 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_DST_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_cpsw0_psil_d_resp_p2p_bridge_safeg_rt_cpsw0_psil_d_resp_bridge_dst_busecc_pend |
3 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_SRC_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_cpsw0_psil_d_resp_p2p_bridge_safeg_rt_cpsw0_psil_d_resp_bridge_src_busecc_pend |
2 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_2_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_edc_ctrl_busecc_2_pend |
1 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_1_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_edc_ctrl_busecc_1_pend |
0 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_0_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_edc_ctrl_busecc_0_pend |
MCU_NAVSS_SEC_ENABLE_SET_REG0 is shown in Figure 10-35 and described in Table 10-159.
Return to Summary Table.
Interrupt Enable Set Register 0
Instance | Physical Address |
---|---|
MCU_NAVSS0_UDMASS_ECCAGGR0 | 2838 1080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
UDMAP0_RPCF1_RAMECC_ENABLE_SET | UDMAP0_RPCF0_RAMECC_ENABLE_SET | UDMAP0_RFFW_RAMECC_ENABLE_SET | UDMAP0_TPCF4_RAMECC_ENABLE_SET | UDMAP0_TPCF1_RAMECC_ENABLE_SET | UDMAP0_TPCF0_RAMECC_ENABLE_SET | UDMAP0_TSTATE_RAMECC_ENABLE_SET | UDMAP0_RPCU_CNTR_RAMECC_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
UDMAP0_RPCU_SB1_RAMECC_ENABLE_SET | UDMAP0_RPCU_SB0_RAMECC_ENABLE_SET | UDMAP0_RPTRCU_CNTR_RAMECC_ENABLE_SET | UDMAP0_RPTRSB2_RAMECC_ENABLE_SET | UDMAP0_RPTRSB1_RAMECC_ENABLE_SET | UDMAP0_RPTRSB0_RAMECC_ENABLE_SET | UDMAP0_TPTRCU_CNTR_RAMECC_ENABLE_SET | UDMAP0_TPTRSB2_RAMECC_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
UDMAP0_TPTRSB1_RAMECC_ENABLE_SET | UDMAP0_TPTRSB0_RAMECC_ENABLE_SET | UDMAP0_RPBUF_PF_RAMECC_ENABLE_SET | UDMAP0_RPBUF_DF_RAMECC_ENABLE_SET | UDMAP0_RPBUF_CF_RAMECC_ENABLE_SET | UDMAP0_RPRQ_RAMECC_ENABLE_SET | UDMAP0_RPCFG_RAMECC_ENABLE_SET | UDMAP0_RPSTATE_RAMECC_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UDMAP0_TPCU_CNTR_RAMECC_ENABLE_SET | UDMAP0_TPCU_RAMECC_ENABLE_SET | UDMAP0_TPBUF_PF_RAMECC_ENABLE_SET | UDMAP0_TPBUF_DF_RAMECC_ENABLE_SET | UDMAP0_TPBUF_CF_RAMECC_ENABLE_SET | UDMAP0_TPCFG_RAMECC_ENABLE_SET | UDMAP0_TPSTATE_RAMECC_ENABLE_SET | ECCAGG_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | UDMAP0_RPCF1_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rpcf1_ramecc_pend |
30 | UDMAP0_RPCF0_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rpcf0_ramecc_pend |
29 | UDMAP0_RFFW_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rffw_ramecc_pend |
28 | UDMAP0_TPCF4_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_tpcf4_ramecc_pend |
27 | UDMAP0_TPCF1_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_tpcf1_ramecc_pend |
26 | UDMAP0_TPCF0_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_tpcf0_ramecc_pend |
25 | UDMAP0_TSTATE_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_tstate_ramecc_pend |
24 | UDMAP0_RPCU_CNTR_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rpcu_cntr_ramecc_pend |
23 | UDMAP0_RPCU_SB1_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rpcu_sb1_ramecc_pend |
22 | UDMAP0_RPCU_SB0_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rpcu_sb0_ramecc_pend |
21 | UDMAP0_RPTRCU_CNTR_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rptrcu_cntr_ramecc_pend |
20 | UDMAP0_RPTRSB2_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rptrsb2_ramecc_pend |
19 | UDMAP0_RPTRSB1_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rptrsb1_ramecc_pend |
18 | UDMAP0_RPTRSB0_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rptrsb0_ramecc_pend |
17 | UDMAP0_TPTRCU_CNTR_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_tptrcu_cntr_ramecc_pend |
16 | UDMAP0_TPTRSB2_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_tptrsb2_ramecc_pend |
15 | UDMAP0_TPTRSB1_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_tptrsb1_ramecc_pend |
14 | UDMAP0_TPTRSB0_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_tptrsb0_ramecc_pend |
13 | UDMAP0_RPBUF_PF_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rpbuf_pf_ramecc_pend |
12 | UDMAP0_RPBUF_DF_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rpbuf_df_ramecc_pend |
11 | UDMAP0_RPBUF_CF_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rpbuf_cf_ramecc_pend |
10 | UDMAP0_RPRQ_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rprq_ramecc_pend |
9 | UDMAP0_RPCFG_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rpcfg_ramecc_pend |
8 | UDMAP0_RPSTATE_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rpstate_ramecc_pend |
7 | UDMAP0_TPCU_CNTR_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_tpcu_cntr_ramecc_pend |
6 | UDMAP0_TPCU_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_tpcu_ramecc_pend |
5 | UDMAP0_TPBUF_PF_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_tpbuf_pf_ramecc_pend |
4 | UDMAP0_TPBUF_DF_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_tpbuf_df_ramecc_pend |
3 | UDMAP0_TPBUF_CF_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_tpbuf_cf_ramecc_pend |
2 | UDMAP0_TPCFG_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_tpcfg_ramecc_pend |
1 | UDMAP0_TPSTATE_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_tpstate_ramecc_pend |
0 | ECCAGG_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for eccagg_pend |
MCU_NAVSS_SEC_ENABLE_SET_REG1 is shown in Figure 10-36 and described in Table 10-161.
Return to Summary Table.
Interrupt Enable Set Register 1
Instance | Physical Address |
---|---|
MCU_NAVSS0_UDMASS_ECCAGGR0 | 2838 1084h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
UDMASS_INTA0_SR_ECC_ENABLE_SET | UDMASS_INTA0_IM_ECC_ENABLE_SET | NAVSS_MCU_UDMASS_UDMASS_INTA0_EDC_CTRL_BUSECC_ENABLE_SET | RINGACC0_ECC_ENABLE_SET | NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_1_ENABLE_SET | NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_0_ENABLE_SET | NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_2_ENABLE_SET | NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_1_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_0_ENABLE_SET | UDMAP0_RRNGOCC_RAMECC_ENABLE_SET | UDMAP0_TRNGOCC_RAMECC_ENABLE_SET | UDMAP0_PSILTID_RAMECC_ENABLE_SET | UDMAP0_PSILR_RAMECC_ENABLE_SET | UDMAP0_SDEC3_RAMECC_ENABLE_SET | UDMAP0_SDEC0_RAMECC_ENABLE_SET | UDMAP0_RDEC2_RAMECC_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
UDMAP0_RDEC1_RAMECC_ENABLE_SET | UDMAP0_RDEC0_RAMECC_ENABLE_SET | UDMAP0_REVTCNTR_RAMECC_ENABLE_SET | UDMAP0_TEVTCNTR_RAMECC_ENABLE_SET | UDMAP0_STS_RAMECC3_ENABLE_SET | UDMAP0_STS_RAMECC2_ENABLE_SET | UDMAP0_STS_RAMECC1_ENABLE_SET | UDMAP0_STS_RAMECC0_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UDMAP0_EH_RAMECC_ENABLE_SET | UDMAP0_PROXY_RAMECC_ENABLE_SET | UDMAP0_RSTATE_RAMECC_ENABLE_SET | UDMAP0_RFLOW1_RAMECC_ENABLE_SET | UDMAP0_RFLOW0_RAMECC_ENABLE_SET | UDMAP0_RPCF4_RAMECC_ENABLE_SET | UDMAP0_RPCF3_RAMECC_ENABLE_SET | UDMAP0_RPCF2_RAMECC_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | UDMASS_INTA0_SR_ECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmass_inta0_sr_ecc_pend |
30 | UDMASS_INTA0_IM_ECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmass_inta0_im_ecc_pend |
29 | NAVSS_MCU_UDMASS_UDMASS_INTA0_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_udmass_inta0_edc_ctrl_busecc_pend |
28 | RINGACC0_ECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ringacc0_ecc_pend |
27 | NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_1_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_1_pend |
26 | NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_0_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_0_pend |
25 | NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_2_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_2_pend |
24 | NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_1_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_1_pend |
23 | NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_0_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_0_pend |
22 | UDMAP0_RRNGOCC_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rrngocc_ramecc_pend |
21 | UDMAP0_TRNGOCC_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_trngocc_ramecc_pend |
20 | UDMAP0_PSILTID_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_psiltid_ramecc_pend |
19 | UDMAP0_PSILR_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_psilr_ramecc_pend |
18 | UDMAP0_SDEC3_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_sdec3_ramecc_pend |
17 | UDMAP0_SDEC0_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_sdec0_ramecc_pend |
16 | UDMAP0_RDEC2_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rdec2_ramecc_pend |
15 | UDMAP0_RDEC1_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rdec1_ramecc_pend |
14 | UDMAP0_RDEC0_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rdec0_ramecc_pend |
13 | UDMAP0_REVTCNTR_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_revtcntr_ramecc_pend |
12 | UDMAP0_TEVTCNTR_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_tevtcntr_ramecc_pend |
11 | UDMAP0_STS_RAMECC3_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_sts_ramecc3_pend |
10 | UDMAP0_STS_RAMECC2_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_sts_ramecc2_pend |
9 | UDMAP0_STS_RAMECC1_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_sts_ramecc1_pend |
8 | UDMAP0_STS_RAMECC0_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_sts_ramecc0_pend |
7 | UDMAP0_EH_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_eh_ramecc_pend |
6 | UDMAP0_PROXY_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_proxy_ramecc_pend |
5 | UDMAP0_RSTATE_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rstate_ramecc_pend |
4 | UDMAP0_RFLOW1_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rflow1_ramecc_pend |
3 | UDMAP0_RFLOW0_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rflow0_ramecc_pend |
2 | UDMAP0_RPCF4_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rpcf4_ramecc_pend |
1 | UDMAP0_RPCF3_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rpcf3_ramecc_pend |
0 | UDMAP0_RPCF2_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rpcf2_ramecc_pend |
MCU_NAVSS_SEC_ENABLE_SET_REG2 is shown in Figure 10-37 and described in Table 10-163.
Return to Summary Table.
Interrupt Enable Set Register 2
Instance | Physical Address |
---|---|
MCU_NAVSS0_UDMASS_ECCAGGR0 | 2838 1088h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_DST_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_SRC_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_DST_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_SRC_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_DST_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_SRC_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_DST_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_SRC_BUSECC_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NAVSS_MCU_UDMASS_PSILSS0_CFG_NAVSS_MCU_UDMASS_PSILSS0_CFG_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_BUSECC_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_EDC_CTRL_BUSECC_ENABLE_SET | UDMASS_INTA0_GC_ECC_ENABLE_SET | UDMASS_INTA0_MC_ECC_ENABLE_SET | UDMASS_INTA0_LC_ECC_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_DST_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_pdma_mcu1_psil_d_data_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_data_bridge_dst_busecc_pend |
30 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_SRC_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_pdma_mcu1_psil_d_data_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_data_bridge_src_busecc_pend |
29 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_DST_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_cpsw0_psil_d_data_p2p_bridge_safeg_rt_cpsw0_psil_d_data_bridge_dst_busecc_pend |
28 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_SRC_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_cpsw0_psil_d_data_p2p_bridge_safeg_rt_cpsw0_psil_d_data_bridge_src_busecc_pend |
27 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_DST_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_pdma_mcu1_psil_s_data_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_data_bridge_dst_busecc_pend |
26 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_SRC_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_pdma_mcu1_psil_s_data_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_data_bridge_src_busecc_pend |
25 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_DST_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_cpsw0_psil_s_data_p2p_bridge_safeg_rt_cpsw0_psil_s_data_bridge_dst_busecc_pend |
24 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_SRC_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_cpsw0_psil_s_data_p2p_bridge_safeg_rt_cpsw0_psil_s_data_bridge_src_busecc_pend |
23 | NAVSS_MCU_UDMASS_PSILSS0_CFG_NAVSS_MCU_UDMASS_PSILSS0_CFG_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cfg_navss_mcu_udmass_psilss0_cfg_edc_ctrl_busecc_pend |
22 | NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_psilcfg0_cfgstrm_navss_mcu_udmass_psilss0_l2p_psilcfg0_cfgstrm_edc_ctrl_busecc_pend |
21 | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_udmap0_cfgstrm_navss_mcu_udmass_psilss0_l2p_udmap0_cfgstrm_edc_ctrl_busecc_pend |
20 | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_udmass_inta0_mevt_in_navss_mcu_udmass_psilss0_l2p_udmass_inta0_mevt_in_edc_ctrl_busecc_pend |
19 | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_udmass_inta0_cevt_navss_mcu_udmass_psilss0_l2p_udmass_inta0_cevt_edc_ctrl_busecc_pend |
18 | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_udmass_inta0_evt_navss_mcu_udmass_psilss0_l2p_udmass_inta0_evt_edc_ctrl_busecc_pend |
17 | NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_dmsc_evt_navss_mcu_udmass_psilss0_l2p_dmsc_evt_edc_ctrl_busecc_pend |
16 | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_udmap0_strm_navss_mcu_udmass_psilss0_l2p_udmap0_strm_edc_ctrl_busecc_pend |
15 | NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_pdma_mcu1_psil_navss_mcu_udmass_psilss0_l2p_pdma_mcu1_psil_edc_ctrl_busecc_pend |
14 | NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_pdma_mcu0_psil_navss_mcu_udmass_psilss0_l2p_pdma_mcu0_psil_edc_ctrl_busecc_pend |
13 | NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_cpsw0_psil_navss_mcu_udmass_psilss0_l2p_cpsw0_psil_edc_ctrl_busecc_pend |
12 | NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_navss_psil_navss_mcu_udmass_psilss0_l2p_navss_psil_edc_ctrl_busecc_pend |
11 | NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_psilcfg0_cfgstrm_bridge_navss_mcu_udmass_psilss0_psilcfg0_cfgstrm_bridge_edc_ctrl_busecc_pend |
10 | NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_udmap0_cfgstrm_bridge_navss_mcu_udmass_psilss0_udmap0_cfgstrm_bridge_edc_ctrl_busecc_pend |
9 | NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_psilcfg0_cfgstrm_safeg_navss_mcu_udmass_psilss0_psilcfg0_cfgstrm_safeg_edc_ctrl_busecc_pend |
8 | NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_udmap0_cfgstrm_safeg_navss_mcu_udmass_psilss0_udmap0_cfgstrm_safeg_edc_ctrl_busecc_pend |
7 | NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_udmap0_strm_safeg_navss_mcu_udmass_psilss0_udmap0_strm_safeg_edc_ctrl_busecc_pend |
6 | NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_pdma_mcu1_psil_safeg_navss_mcu_udmass_psilss0_pdma_mcu1_psil_safeg_edc_ctrl_busecc_pend |
5 | NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_pdma_mcu0_psil_safeg_navss_mcu_udmass_psilss0_pdma_mcu0_psil_safeg_edc_ctrl_busecc_pend |
4 | NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cpsw0_psil_safeg_navss_mcu_udmass_psilss0_cpsw0_psil_safeg_edc_ctrl_busecc_pend |
3 | NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_navss_psil_rt_bridge_navss_mcu_udmass_psilss0_navss_psil_rt_bridge_edc_ctrl_busecc_pend |
2 | UDMASS_INTA0_GC_ECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmass_inta0_gc_ecc_pend |
1 | UDMASS_INTA0_MC_ECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmass_inta0_mc_ecc_pend |
0 | UDMASS_INTA0_LC_ECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmass_inta0_lc_ecc_pend |
MCU_NAVSS_SEC_ENABLE_SET_REG3 is shown in Figure 10-38 and described in Table 10-165.
Return to Summary Table.
Interrupt Enable Set Register 3
Instance | Physical Address |
---|---|
MCU_NAVSS0_UDMASS_ECCAGGR0 | 2838 108Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_D_DEF_EVT_BRIDGE_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_DST_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_SRC_BUSECC_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_DST_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_SRC_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_DST_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_SRC_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_DST_BUSECC_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_SRC_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_DST_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_SRC_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_DST_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_SRC_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R/W | X | |
23 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_edc_ctrl_busecc_4_pend |
22 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_edc_ctrl_busecc_3_pend |
21 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_edc_ctrl_busecc_2_pend |
20 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_edc_ctrl_busecc_1_pend |
19 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_edc_ctrl_busecc_0_pend |
18 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_D_DEF_EVT_BRIDGE_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_d_def_evt_p2p_bridge_d_def_evt_bridge_busecc_pend |
17 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_DST_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_safeg_rt_pdma_mcu1_psil_d_etl0_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_etl0_bridge_dst_busecc_pend |
16 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_SRC_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_safeg_rt_pdma_mcu1_psil_d_etl0_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_etl0_bridge_src_busecc_pend |
15 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_DST_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_safeg_rt_pdma_mcu1_psil_s_etl0_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_etl0_bridge_dst_busecc_pend |
14 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_SRC_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_safeg_rt_pdma_mcu1_psil_s_etl0_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_etl0_bridge_src_busecc_pend |
13 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_edc_ctrl_busecc_2_pend |
12 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_edc_ctrl_busecc_1_pend |
11 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_edc_ctrl_busecc_0_pend |
10 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_DST_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_pdma_mcu1_psil_s_resp_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_resp_bridge_dst_busecc_pend |
9 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_SRC_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_pdma_mcu1_psil_s_resp_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_resp_bridge_src_busecc_pend |
8 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_DST_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_cpsw0_psil_s_resp_p2p_bridge_safeg_rt_cpsw0_psil_s_resp_bridge_dst_busecc_pend |
7 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_SRC_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_cpsw0_psil_s_resp_p2p_bridge_safeg_rt_cpsw0_psil_s_resp_bridge_src_busecc_pend |
6 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_DST_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_pdma_mcu1_psil_d_resp_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_resp_bridge_dst_busecc_pend |
5 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_SRC_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_pdma_mcu1_psil_d_resp_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_resp_bridge_src_busecc_pend |
4 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_DST_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_cpsw0_psil_d_resp_p2p_bridge_safeg_rt_cpsw0_psil_d_resp_bridge_dst_busecc_pend |
3 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_SRC_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_cpsw0_psil_d_resp_p2p_bridge_safeg_rt_cpsw0_psil_d_resp_bridge_src_busecc_pend |
2 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_edc_ctrl_busecc_2_pend |
1 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_edc_ctrl_busecc_1_pend |
0 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_edc_ctrl_busecc_0_pend |
MCU_NAVSS_SEC_ENABLE_CLR_REG0 is shown in Figure 10-39 and described in Table 10-167.
Return to Summary Table.
Interrupt Enable Clear Register 0
Instance | Physical Address |
---|---|
MCU_NAVSS0_UDMASS_ECCAGGR0 | 2838 10C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
UDMAP0_RPCF1_RAMECC_ENABLE_CLR | UDMAP0_RPCF0_RAMECC_ENABLE_CLR | UDMAP0_RFFW_RAMECC_ENABLE_CLR | UDMAP0_TPCF4_RAMECC_ENABLE_CLR | UDMAP0_TPCF1_RAMECC_ENABLE_CLR | UDMAP0_TPCF0_RAMECC_ENABLE_CLR | UDMAP0_TSTATE_RAMECC_ENABLE_CLR | UDMAP0_RPCU_CNTR_RAMECC_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
UDMAP0_RPCU_SB1_RAMECC_ENABLE_CLR | UDMAP0_RPCU_SB0_RAMECC_ENABLE_CLR | UDMAP0_RPTRCU_CNTR_RAMECC_ENABLE_CLR | UDMAP0_RPTRSB2_RAMECC_ENABLE_CLR | UDMAP0_RPTRSB1_RAMECC_ENABLE_CLR | UDMAP0_RPTRSB0_RAMECC_ENABLE_CLR | UDMAP0_TPTRCU_CNTR_RAMECC_ENABLE_CLR | UDMAP0_TPTRSB2_RAMECC_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
UDMAP0_TPTRSB1_RAMECC_ENABLE_CLR | UDMAP0_TPTRSB0_RAMECC_ENABLE_CLR | UDMAP0_RPBUF_PF_RAMECC_ENABLE_CLR | UDMAP0_RPBUF_DF_RAMECC_ENABLE_CLR | UDMAP0_RPBUF_CF_RAMECC_ENABLE_CLR | UDMAP0_RPRQ_RAMECC_ENABLE_CLR | UDMAP0_RPCFG_RAMECC_ENABLE_CLR | UDMAP0_RPSTATE_RAMECC_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UDMAP0_TPCU_CNTR_RAMECC_ENABLE_CLR | UDMAP0_TPCU_RAMECC_ENABLE_CLR | UDMAP0_TPBUF_PF_RAMECC_ENABLE_CLR | UDMAP0_TPBUF_DF_RAMECC_ENABLE_CLR | UDMAP0_TPBUF_CF_RAMECC_ENABLE_CLR | UDMAP0_TPCFG_RAMECC_ENABLE_CLR | UDMAP0_TPSTATE_RAMECC_ENABLE_CLR | ECCAGG_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | UDMAP0_RPCF1_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rpcf1_ramecc_pend |
30 | UDMAP0_RPCF0_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rpcf0_ramecc_pend |
29 | UDMAP0_RFFW_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rffw_ramecc_pend |
28 | UDMAP0_TPCF4_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_tpcf4_ramecc_pend |
27 | UDMAP0_TPCF1_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_tpcf1_ramecc_pend |
26 | UDMAP0_TPCF0_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_tpcf0_ramecc_pend |
25 | UDMAP0_TSTATE_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_tstate_ramecc_pend |
24 | UDMAP0_RPCU_CNTR_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rpcu_cntr_ramecc_pend |
23 | UDMAP0_RPCU_SB1_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rpcu_sb1_ramecc_pend |
22 | UDMAP0_RPCU_SB0_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rpcu_sb0_ramecc_pend |
21 | UDMAP0_RPTRCU_CNTR_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rptrcu_cntr_ramecc_pend |
20 | UDMAP0_RPTRSB2_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rptrsb2_ramecc_pend |
19 | UDMAP0_RPTRSB1_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rptrsb1_ramecc_pend |
18 | UDMAP0_RPTRSB0_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rptrsb0_ramecc_pend |
17 | UDMAP0_TPTRCU_CNTR_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_tptrcu_cntr_ramecc_pend |
16 | UDMAP0_TPTRSB2_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_tptrsb2_ramecc_pend |
15 | UDMAP0_TPTRSB1_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_tptrsb1_ramecc_pend |
14 | UDMAP0_TPTRSB0_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_tptrsb0_ramecc_pend |
13 | UDMAP0_RPBUF_PF_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rpbuf_pf_ramecc_pend |
12 | UDMAP0_RPBUF_DF_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rpbuf_df_ramecc_pend |
11 | UDMAP0_RPBUF_CF_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rpbuf_cf_ramecc_pend |
10 | UDMAP0_RPRQ_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rprq_ramecc_pend |
9 | UDMAP0_RPCFG_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rpcfg_ramecc_pend |
8 | UDMAP0_RPSTATE_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rpstate_ramecc_pend |
7 | UDMAP0_TPCU_CNTR_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_tpcu_cntr_ramecc_pend |
6 | UDMAP0_TPCU_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_tpcu_ramecc_pend |
5 | UDMAP0_TPBUF_PF_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_tpbuf_pf_ramecc_pend |
4 | UDMAP0_TPBUF_DF_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_tpbuf_df_ramecc_pend |
3 | UDMAP0_TPBUF_CF_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_tpbuf_cf_ramecc_pend |
2 | UDMAP0_TPCFG_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_tpcfg_ramecc_pend |
1 | UDMAP0_TPSTATE_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_tpstate_ramecc_pend |
0 | ECCAGG_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for eccagg_pend |
MCU_NAVSS_SEC_ENABLE_CLR_REG1 is shown in Figure 10-40 and described in Table 10-169.
Return to Summary Table.
Interrupt Enable Clear Register 1
Instance | Physical Address |
---|---|
MCU_NAVSS0_UDMASS_ECCAGGR0 | 2838 10C4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
UDMASS_INTA0_SR_ECC_ENABLE_CLR | UDMASS_INTA0_IM_ECC_ENABLE_CLR | NAVSS_MCU_UDMASS_UDMASS_INTA0_EDC_CTRL_BUSECC_ENABLE_CLR | RINGACC0_ECC_ENABLE_CLR | NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_1_ENABLE_CLR | NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_0_ENABLE_CLR | NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_2_ENABLE_CLR | NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_1_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_0_ENABLE_CLR | UDMAP0_RRNGOCC_RAMECC_ENABLE_CLR | UDMAP0_TRNGOCC_RAMECC_ENABLE_CLR | UDMAP0_PSILTID_RAMECC_ENABLE_CLR | UDMAP0_PSILR_RAMECC_ENABLE_CLR | UDMAP0_SDEC3_RAMECC_ENABLE_CLR | UDMAP0_SDEC0_RAMECC_ENABLE_CLR | UDMAP0_RDEC2_RAMECC_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
UDMAP0_RDEC1_RAMECC_ENABLE_CLR | UDMAP0_RDEC0_RAMECC_ENABLE_CLR | UDMAP0_REVTCNTR_RAMECC_ENABLE_CLR | UDMAP0_TEVTCNTR_RAMECC_ENABLE_CLR | UDMAP0_STS_RAMECC3_ENABLE_CLR | UDMAP0_STS_RAMECC2_ENABLE_CLR | UDMAP0_STS_RAMECC1_ENABLE_CLR | UDMAP0_STS_RAMECC0_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UDMAP0_EH_RAMECC_ENABLE_CLR | UDMAP0_PROXY_RAMECC_ENABLE_CLR | UDMAP0_RSTATE_RAMECC_ENABLE_CLR | UDMAP0_RFLOW1_RAMECC_ENABLE_CLR | UDMAP0_RFLOW0_RAMECC_ENABLE_CLR | UDMAP0_RPCF4_RAMECC_ENABLE_CLR | UDMAP0_RPCF3_RAMECC_ENABLE_CLR | UDMAP0_RPCF2_RAMECC_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | UDMASS_INTA0_SR_ECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmass_inta0_sr_ecc_pend |
30 | UDMASS_INTA0_IM_ECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmass_inta0_im_ecc_pend |
29 | NAVSS_MCU_UDMASS_UDMASS_INTA0_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_udmass_inta0_edc_ctrl_busecc_pend |
28 | RINGACC0_ECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ringacc0_ecc_pend |
27 | NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_1_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_1_pend |
26 | NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_0_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_0_pend |
25 | NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_2_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_2_pend |
24 | NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_1_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_1_pend |
23 | NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_0_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_0_pend |
22 | UDMAP0_RRNGOCC_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rrngocc_ramecc_pend |
21 | UDMAP0_TRNGOCC_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_trngocc_ramecc_pend |
20 | UDMAP0_PSILTID_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_psiltid_ramecc_pend |
19 | UDMAP0_PSILR_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_psilr_ramecc_pend |
18 | UDMAP0_SDEC3_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_sdec3_ramecc_pend |
17 | UDMAP0_SDEC0_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_sdec0_ramecc_pend |
16 | UDMAP0_RDEC2_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rdec2_ramecc_pend |
15 | UDMAP0_RDEC1_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rdec1_ramecc_pend |
14 | UDMAP0_RDEC0_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rdec0_ramecc_pend |
13 | UDMAP0_REVTCNTR_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_revtcntr_ramecc_pend |
12 | UDMAP0_TEVTCNTR_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_tevtcntr_ramecc_pend |
11 | UDMAP0_STS_RAMECC3_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_sts_ramecc3_pend |
10 | UDMAP0_STS_RAMECC2_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_sts_ramecc2_pend |
9 | UDMAP0_STS_RAMECC1_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_sts_ramecc1_pend |
8 | UDMAP0_STS_RAMECC0_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_sts_ramecc0_pend |
7 | UDMAP0_EH_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_eh_ramecc_pend |
6 | UDMAP0_PROXY_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_proxy_ramecc_pend |
5 | UDMAP0_RSTATE_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rstate_ramecc_pend |
4 | UDMAP0_RFLOW1_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rflow1_ramecc_pend |
3 | UDMAP0_RFLOW0_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rflow0_ramecc_pend |
2 | UDMAP0_RPCF4_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rpcf4_ramecc_pend |
1 | UDMAP0_RPCF3_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rpcf3_ramecc_pend |
0 | UDMAP0_RPCF2_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rpcf2_ramecc_pend |
MCU_NAVSS_SEC_ENABLE_CLR_REG2 is shown in Figure 10-41 and described in Table 10-171.
Return to Summary Table.
Interrupt Enable Clear Register 2
Instance | Physical Address |
---|---|
MCU_NAVSS0_UDMASS_ECCAGGR0 | 2838 10C8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_DST_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_SRC_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_DST_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_SRC_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_DST_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_SRC_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_DST_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_SRC_BUSECC_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NAVSS_MCU_UDMASS_PSILSS0_CFG_NAVSS_MCU_UDMASS_PSILSS0_CFG_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_BUSECC_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_EDC_CTRL_BUSECC_ENABLE_CLR | UDMASS_INTA0_GC_ECC_ENABLE_CLR | UDMASS_INTA0_MC_ECC_ENABLE_CLR | UDMASS_INTA0_LC_ECC_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_DST_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_pdma_mcu1_psil_d_data_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_data_bridge_dst_busecc_pend |
30 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_SRC_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_pdma_mcu1_psil_d_data_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_data_bridge_src_busecc_pend |
29 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_DST_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_cpsw0_psil_d_data_p2p_bridge_safeg_rt_cpsw0_psil_d_data_bridge_dst_busecc_pend |
28 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_SRC_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_cpsw0_psil_d_data_p2p_bridge_safeg_rt_cpsw0_psil_d_data_bridge_src_busecc_pend |
27 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_DST_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_pdma_mcu1_psil_s_data_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_data_bridge_dst_busecc_pend |
26 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_SRC_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_pdma_mcu1_psil_s_data_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_data_bridge_src_busecc_pend |
25 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_DST_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_cpsw0_psil_s_data_p2p_bridge_safeg_rt_cpsw0_psil_s_data_bridge_dst_busecc_pend |
24 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_SRC_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_cpsw0_psil_s_data_p2p_bridge_safeg_rt_cpsw0_psil_s_data_bridge_src_busecc_pend |
23 | NAVSS_MCU_UDMASS_PSILSS0_CFG_NAVSS_MCU_UDMASS_PSILSS0_CFG_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cfg_navss_mcu_udmass_psilss0_cfg_edc_ctrl_busecc_pend |
22 | NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_psilcfg0_cfgstrm_navss_mcu_udmass_psilss0_l2p_psilcfg0_cfgstrm_edc_ctrl_busecc_pend |
21 | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_udmap0_cfgstrm_navss_mcu_udmass_psilss0_l2p_udmap0_cfgstrm_edc_ctrl_busecc_pend |
20 | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_udmass_inta0_mevt_in_navss_mcu_udmass_psilss0_l2p_udmass_inta0_mevt_in_edc_ctrl_busecc_pend |
19 | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_udmass_inta0_cevt_navss_mcu_udmass_psilss0_l2p_udmass_inta0_cevt_edc_ctrl_busecc_pend |
18 | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_udmass_inta0_evt_navss_mcu_udmass_psilss0_l2p_udmass_inta0_evt_edc_ctrl_busecc_pend |
17 | NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_dmsc_evt_navss_mcu_udmass_psilss0_l2p_dmsc_evt_edc_ctrl_busecc_pend |
16 | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_udmap0_strm_navss_mcu_udmass_psilss0_l2p_udmap0_strm_edc_ctrl_busecc_pend |
15 | NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_pdma_mcu1_psil_navss_mcu_udmass_psilss0_l2p_pdma_mcu1_psil_edc_ctrl_busecc_pend |
14 | NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_pdma_mcu0_psil_navss_mcu_udmass_psilss0_l2p_pdma_mcu0_psil_edc_ctrl_busecc_pend |
13 | NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_cpsw0_psil_navss_mcu_udmass_psilss0_l2p_cpsw0_psil_edc_ctrl_busecc_pend |
12 | NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_navss_psil_navss_mcu_udmass_psilss0_l2p_navss_psil_edc_ctrl_busecc_pend |
11 | NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_psilcfg0_cfgstrm_bridge_navss_mcu_udmass_psilss0_psilcfg0_cfgstrm_bridge_edc_ctrl_busecc_pend |
10 | NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_udmap0_cfgstrm_bridge_navss_mcu_udmass_psilss0_udmap0_cfgstrm_bridge_edc_ctrl_busecc_pend |
9 | NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_psilcfg0_cfgstrm_safeg_navss_mcu_udmass_psilss0_psilcfg0_cfgstrm_safeg_edc_ctrl_busecc_pend |
8 | NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_udmap0_cfgstrm_safeg_navss_mcu_udmass_psilss0_udmap0_cfgstrm_safeg_edc_ctrl_busecc_pend |
7 | NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_udmap0_strm_safeg_navss_mcu_udmass_psilss0_udmap0_strm_safeg_edc_ctrl_busecc_pend |
6 | NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_pdma_mcu1_psil_safeg_navss_mcu_udmass_psilss0_pdma_mcu1_psil_safeg_edc_ctrl_busecc_pend |
5 | NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_pdma_mcu0_psil_safeg_navss_mcu_udmass_psilss0_pdma_mcu0_psil_safeg_edc_ctrl_busecc_pend |
4 | NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cpsw0_psil_safeg_navss_mcu_udmass_psilss0_cpsw0_psil_safeg_edc_ctrl_busecc_pend |
3 | NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_navss_psil_rt_bridge_navss_mcu_udmass_psilss0_navss_psil_rt_bridge_edc_ctrl_busecc_pend |
2 | UDMASS_INTA0_GC_ECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmass_inta0_gc_ecc_pend |
1 | UDMASS_INTA0_MC_ECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmass_inta0_mc_ecc_pend |
0 | UDMASS_INTA0_LC_ECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmass_inta0_lc_ecc_pend |
MCU_NAVSS_SEC_ENABLE_CLR_REG3 is shown in Figure 10-42 and described in Table 10-173.
Return to Summary Table.
Interrupt Enable Clear Register 3
Instance | Physical Address |
---|---|
MCU_NAVSS0_UDMASS_ECCAGGR0 | 2838 10CCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_D_DEF_EVT_BRIDGE_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_DST_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_SRC_BUSECC_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_DST_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_SRC_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_DST_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_SRC_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_DST_BUSECC_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_SRC_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_DST_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_SRC_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_DST_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_SRC_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R/W | X | |
23 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_edc_ctrl_busecc_4_pend |
22 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_edc_ctrl_busecc_3_pend |
21 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_edc_ctrl_busecc_2_pend |
20 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_edc_ctrl_busecc_1_pend |
19 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_edc_ctrl_busecc_0_pend |
18 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_D_DEF_EVT_BRIDGE_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_d_def_evt_p2p_bridge_d_def_evt_bridge_busecc_pend |
17 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_DST_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_safeg_rt_pdma_mcu1_psil_d_etl0_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_etl0_bridge_dst_busecc_pend |
16 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_SRC_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_safeg_rt_pdma_mcu1_psil_d_etl0_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_etl0_bridge_src_busecc_pend |
15 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_DST_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_safeg_rt_pdma_mcu1_psil_s_etl0_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_etl0_bridge_dst_busecc_pend |
14 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_SRC_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_safeg_rt_pdma_mcu1_psil_s_etl0_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_etl0_bridge_src_busecc_pend |
13 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_edc_ctrl_busecc_2_pend |
12 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_edc_ctrl_busecc_1_pend |
11 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_edc_ctrl_busecc_0_pend |
10 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_DST_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_pdma_mcu1_psil_s_resp_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_resp_bridge_dst_busecc_pend |
9 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_SRC_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_pdma_mcu1_psil_s_resp_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_resp_bridge_src_busecc_pend |
8 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_DST_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_cpsw0_psil_s_resp_p2p_bridge_safeg_rt_cpsw0_psil_s_resp_bridge_dst_busecc_pend |
7 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_SRC_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_cpsw0_psil_s_resp_p2p_bridge_safeg_rt_cpsw0_psil_s_resp_bridge_src_busecc_pend |
6 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_DST_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_pdma_mcu1_psil_d_resp_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_resp_bridge_dst_busecc_pend |
5 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_SRC_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_pdma_mcu1_psil_d_resp_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_resp_bridge_src_busecc_pend |
4 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_DST_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_cpsw0_psil_d_resp_p2p_bridge_safeg_rt_cpsw0_psil_d_resp_bridge_dst_busecc_pend |
3 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_SRC_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_cpsw0_psil_d_resp_p2p_bridge_safeg_rt_cpsw0_psil_d_resp_bridge_src_busecc_pend |
2 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_edc_ctrl_busecc_2_pend |
1 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_edc_ctrl_busecc_1_pend |
0 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_edc_ctrl_busecc_0_pend |
MCU_NAVSS_DED_EOI_REG is shown in Figure 10-43 and described in Table 10-175.
Return to Summary Table.
EOI Register
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
MCU_NAVSS0_UDMASS_ECCAGGR0 | 2838 113Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R/W-X | R/W1S-0h | ||||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | EOI_WR | R/W1S | 0h | EOI Register |
MCU_NAVSS_DED_STATUS_REG0 is shown in Figure 10-44 and described in Table 10-177.
Return to Summary Table.
Interrupt Status Register 0
Instance | Physical Address |
---|---|
MCU_NAVSS0_UDMASS_ECCAGGR0 | 2838 1140h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
UDMAP0_RPCF1_RAMECC_PEND | UDMAP0_RPCF0_RAMECC_PEND | UDMAP0_RFFW_RAMECC_PEND | UDMAP0_TPCF4_RAMECC_PEND | UDMAP0_TPCF1_RAMECC_PEND | UDMAP0_TPCF0_RAMECC_PEND | UDMAP0_TSTATE_RAMECC_PEND | UDMAP0_RPCU_CNTR_RAMECC_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
UDMAP0_RPCU_SB1_RAMECC_PEND | UDMAP0_RPCU_SB0_RAMECC_PEND | UDMAP0_RPTRCU_CNTR_RAMECC_PEND | UDMAP0_RPTRSB2_RAMECC_PEND | UDMAP0_RPTRSB1_RAMECC_PEND | UDMAP0_RPTRSB0_RAMECC_PEND | UDMAP0_TPTRCU_CNTR_RAMECC_PEND | UDMAP0_TPTRSB2_RAMECC_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
UDMAP0_TPTRSB1_RAMECC_PEND | UDMAP0_TPTRSB0_RAMECC_PEND | UDMAP0_RPBUF_PF_RAMECC_PEND | UDMAP0_RPBUF_DF_RAMECC_PEND | UDMAP0_RPBUF_CF_RAMECC_PEND | UDMAP0_RPRQ_RAMECC_PEND | UDMAP0_RPCFG_RAMECC_PEND | UDMAP0_RPSTATE_RAMECC_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UDMAP0_TPCU_CNTR_RAMECC_PEND | UDMAP0_TPCU_RAMECC_PEND | UDMAP0_TPBUF_PF_RAMECC_PEND | UDMAP0_TPBUF_DF_RAMECC_PEND | UDMAP0_TPBUF_CF_RAMECC_PEND | UDMAP0_TPCFG_RAMECC_PEND | UDMAP0_TPSTATE_RAMECC_PEND | ECCAGG_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | UDMAP0_RPCF1_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rpcf1_ramecc_pend |
30 | UDMAP0_RPCF0_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rpcf0_ramecc_pend |
29 | UDMAP0_RFFW_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rffw_ramecc_pend |
28 | UDMAP0_TPCF4_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_tpcf4_ramecc_pend |
27 | UDMAP0_TPCF1_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_tpcf1_ramecc_pend |
26 | UDMAP0_TPCF0_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_tpcf0_ramecc_pend |
25 | UDMAP0_TSTATE_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_tstate_ramecc_pend |
24 | UDMAP0_RPCU_CNTR_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rpcu_cntr_ramecc_pend |
23 | UDMAP0_RPCU_SB1_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rpcu_sb1_ramecc_pend |
22 | UDMAP0_RPCU_SB0_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rpcu_sb0_ramecc_pend |
21 | UDMAP0_RPTRCU_CNTR_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rptrcu_cntr_ramecc_pend |
20 | UDMAP0_RPTRSB2_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rptrsb2_ramecc_pend |
19 | UDMAP0_RPTRSB1_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rptrsb1_ramecc_pend |
18 | UDMAP0_RPTRSB0_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rptrsb0_ramecc_pend |
17 | UDMAP0_TPTRCU_CNTR_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_tptrcu_cntr_ramecc_pend |
16 | UDMAP0_TPTRSB2_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_tptrsb2_ramecc_pend |
15 | UDMAP0_TPTRSB1_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_tptrsb1_ramecc_pend |
14 | UDMAP0_TPTRSB0_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_tptrsb0_ramecc_pend |
13 | UDMAP0_RPBUF_PF_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rpbuf_pf_ramecc_pend |
12 | UDMAP0_RPBUF_DF_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rpbuf_df_ramecc_pend |
11 | UDMAP0_RPBUF_CF_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rpbuf_cf_ramecc_pend |
10 | UDMAP0_RPRQ_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rprq_ramecc_pend |
9 | UDMAP0_RPCFG_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rpcfg_ramecc_pend |
8 | UDMAP0_RPSTATE_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rpstate_ramecc_pend |
7 | UDMAP0_TPCU_CNTR_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_tpcu_cntr_ramecc_pend |
6 | UDMAP0_TPCU_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_tpcu_ramecc_pend |
5 | UDMAP0_TPBUF_PF_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_tpbuf_pf_ramecc_pend |
4 | UDMAP0_TPBUF_DF_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_tpbuf_df_ramecc_pend |
3 | UDMAP0_TPBUF_CF_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_tpbuf_cf_ramecc_pend |
2 | UDMAP0_TPCFG_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_tpcfg_ramecc_pend |
1 | UDMAP0_TPSTATE_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_tpstate_ramecc_pend |
0 | ECCAGG_PEND | R/W1S | 0h | Interrupt Pending Status for eccagg_pend |
MCU_NAVSS_DED_STATUS_REG1 is shown in Figure 10-45 and described in Table 10-179.
Return to Summary Table.
Interrupt Status Register 1
Instance | Physical Address |
---|---|
MCU_NAVSS0_UDMASS_ECCAGGR0 | 2838 1144h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
UDMASS_INTA0_SR_ECC_PEND | UDMASS_INTA0_IM_ECC_PEND | NAVSS_MCU_UDMASS_UDMASS_INTA0_EDC_CTRL_BUSECC_PEND | RINGACC0_ECC_PEND | NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_1_PEND | NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_0_PEND | NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_2_PEND | NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_1_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_0_PEND | UDMAP0_RRNGOCC_RAMECC_PEND | UDMAP0_TRNGOCC_RAMECC_PEND | UDMAP0_PSILTID_RAMECC_PEND | UDMAP0_PSILR_RAMECC_PEND | UDMAP0_SDEC3_RAMECC_PEND | UDMAP0_SDEC0_RAMECC_PEND | UDMAP0_RDEC2_RAMECC_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
UDMAP0_RDEC1_RAMECC_PEND | UDMAP0_RDEC0_RAMECC_PEND | UDMAP0_REVTCNTR_RAMECC_PEND | UDMAP0_TEVTCNTR_RAMECC_PEND | UDMAP0_STS_RAMECC3_PEND | UDMAP0_STS_RAMECC2_PEND | UDMAP0_STS_RAMECC1_PEND | UDMAP0_STS_RAMECC0_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UDMAP0_EH_RAMECC_PEND | UDMAP0_PROXY_RAMECC_PEND | UDMAP0_RSTATE_RAMECC_PEND | UDMAP0_RFLOW1_RAMECC_PEND | UDMAP0_RFLOW0_RAMECC_PEND | UDMAP0_RPCF4_RAMECC_PEND | UDMAP0_RPCF3_RAMECC_PEND | UDMAP0_RPCF2_RAMECC_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | UDMASS_INTA0_SR_ECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmass_inta0_sr_ecc_pend |
30 | UDMASS_INTA0_IM_ECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmass_inta0_im_ecc_pend |
29 | NAVSS_MCU_UDMASS_UDMASS_INTA0_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_udmass_inta0_edc_ctrl_busecc_pend |
28 | RINGACC0_ECC_PEND | R/W1S | 0h | Interrupt Pending Status for ringacc0_ecc_pend |
27 | NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_1_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_1_pend |
26 | NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_0_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_0_pend |
25 | NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_2_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_udmap0_edc_ctrl_busecc_2_pend |
24 | NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_1_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_udmap0_edc_ctrl_busecc_1_pend |
23 | NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_0_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_udmap0_edc_ctrl_busecc_0_pend |
22 | UDMAP0_RRNGOCC_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rrngocc_ramecc_pend |
21 | UDMAP0_TRNGOCC_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_trngocc_ramecc_pend |
20 | UDMAP0_PSILTID_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_psiltid_ramecc_pend |
19 | UDMAP0_PSILR_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_psilr_ramecc_pend |
18 | UDMAP0_SDEC3_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_sdec3_ramecc_pend |
17 | UDMAP0_SDEC0_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_sdec0_ramecc_pend |
16 | UDMAP0_RDEC2_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rdec2_ramecc_pend |
15 | UDMAP0_RDEC1_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rdec1_ramecc_pend |
14 | UDMAP0_RDEC0_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rdec0_ramecc_pend |
13 | UDMAP0_REVTCNTR_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_revtcntr_ramecc_pend |
12 | UDMAP0_TEVTCNTR_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_tevtcntr_ramecc_pend |
11 | UDMAP0_STS_RAMECC3_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_sts_ramecc3_pend |
10 | UDMAP0_STS_RAMECC2_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_sts_ramecc2_pend |
9 | UDMAP0_STS_RAMECC1_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_sts_ramecc1_pend |
8 | UDMAP0_STS_RAMECC0_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_sts_ramecc0_pend |
7 | UDMAP0_EH_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_eh_ramecc_pend |
6 | UDMAP0_PROXY_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_proxy_ramecc_pend |
5 | UDMAP0_RSTATE_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rstate_ramecc_pend |
4 | UDMAP0_RFLOW1_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rflow1_ramecc_pend |
3 | UDMAP0_RFLOW0_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rflow0_ramecc_pend |
2 | UDMAP0_RPCF4_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rpcf4_ramecc_pend |
1 | UDMAP0_RPCF3_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rpcf3_ramecc_pend |
0 | UDMAP0_RPCF2_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmap0_rpcf2_ramecc_pend |
MCU_NAVSS_DED_STATUS_REG2 is shown in Figure 10-46 and described in Table 10-181.
Return to Summary Table.
Interrupt Status Register 2
Instance | Physical Address |
---|---|
MCU_NAVSS0_UDMASS_ECCAGGR0 | 2838 1148h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_DST_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_SRC_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_DST_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_SRC_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_DST_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_SRC_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_DST_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_SRC_BUSECC_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NAVSS_MCU_UDMASS_PSILSS0_CFG_NAVSS_MCU_UDMASS_PSILSS0_CFG_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_BUSECC_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_EDC_CTRL_BUSECC_PEND | UDMASS_INTA0_GC_ECC_PEND | UDMASS_INTA0_MC_ECC_PEND | UDMASS_INTA0_LC_ECC_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_DST_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_pdma_mcu1_psil_d_data_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_data_bridge_dst_busecc_pend |
30 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_SRC_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_pdma_mcu1_psil_d_data_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_data_bridge_src_busecc_pend |
29 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_DST_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_cpsw0_psil_d_data_p2p_bridge_safeg_rt_cpsw0_psil_d_data_bridge_dst_busecc_pend |
28 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_SRC_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_cpsw0_psil_d_data_p2p_bridge_safeg_rt_cpsw0_psil_d_data_bridge_src_busecc_pend |
27 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_DST_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_pdma_mcu1_psil_s_data_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_data_bridge_dst_busecc_pend |
26 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_SRC_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_pdma_mcu1_psil_s_data_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_data_bridge_src_busecc_pend |
25 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_DST_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_cpsw0_psil_s_data_p2p_bridge_safeg_rt_cpsw0_psil_s_data_bridge_dst_busecc_pend |
24 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_SRC_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_cpsw0_psil_s_data_p2p_bridge_safeg_rt_cpsw0_psil_s_data_bridge_src_busecc_pend |
23 | NAVSS_MCU_UDMASS_PSILSS0_CFG_NAVSS_MCU_UDMASS_PSILSS0_CFG_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cfg_navss_mcu_udmass_psilss0_cfg_edc_ctrl_busecc_pend |
22 | NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_psilcfg0_cfgstrm_navss_mcu_udmass_psilss0_l2p_psilcfg0_cfgstrm_edc_ctrl_busecc_pend |
21 | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_udmap0_cfgstrm_navss_mcu_udmass_psilss0_l2p_udmap0_cfgstrm_edc_ctrl_busecc_pend |
20 | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_udmass_inta0_mevt_in_navss_mcu_udmass_psilss0_l2p_udmass_inta0_mevt_in_edc_ctrl_busecc_pend |
19 | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_udmass_inta0_cevt_navss_mcu_udmass_psilss0_l2p_udmass_inta0_cevt_edc_ctrl_busecc_pend |
18 | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_udmass_inta0_evt_navss_mcu_udmass_psilss0_l2p_udmass_inta0_evt_edc_ctrl_busecc_pend |
17 | NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_dmsc_evt_navss_mcu_udmass_psilss0_l2p_dmsc_evt_edc_ctrl_busecc_pend |
16 | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_udmap0_strm_navss_mcu_udmass_psilss0_l2p_udmap0_strm_edc_ctrl_busecc_pend |
15 | NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_pdma_mcu1_psil_navss_mcu_udmass_psilss0_l2p_pdma_mcu1_psil_edc_ctrl_busecc_pend |
14 | NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_pdma_mcu0_psil_navss_mcu_udmass_psilss0_l2p_pdma_mcu0_psil_edc_ctrl_busecc_pend |
13 | NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_cpsw0_psil_navss_mcu_udmass_psilss0_l2p_cpsw0_psil_edc_ctrl_busecc_pend |
12 | NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_navss_psil_navss_mcu_udmass_psilss0_l2p_navss_psil_edc_ctrl_busecc_pend |
11 | NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_psilcfg0_cfgstrm_bridge_navss_mcu_udmass_psilss0_psilcfg0_cfgstrm_bridge_edc_ctrl_busecc_pend |
10 | NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_udmap0_cfgstrm_bridge_navss_mcu_udmass_psilss0_udmap0_cfgstrm_bridge_edc_ctrl_busecc_pend |
9 | NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_psilcfg0_cfgstrm_safeg_navss_mcu_udmass_psilss0_psilcfg0_cfgstrm_safeg_edc_ctrl_busecc_pend |
8 | NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_udmap0_cfgstrm_safeg_navss_mcu_udmass_psilss0_udmap0_cfgstrm_safeg_edc_ctrl_busecc_pend |
7 | NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_udmap0_strm_safeg_navss_mcu_udmass_psilss0_udmap0_strm_safeg_edc_ctrl_busecc_pend |
6 | NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_pdma_mcu1_psil_safeg_navss_mcu_udmass_psilss0_pdma_mcu1_psil_safeg_edc_ctrl_busecc_pend |
5 | NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_pdma_mcu0_psil_safeg_navss_mcu_udmass_psilss0_pdma_mcu0_psil_safeg_edc_ctrl_busecc_pend |
4 | NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cpsw0_psil_safeg_navss_mcu_udmass_psilss0_cpsw0_psil_safeg_edc_ctrl_busecc_pend |
3 | NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_navss_psil_rt_bridge_navss_mcu_udmass_psilss0_navss_psil_rt_bridge_edc_ctrl_busecc_pend |
2 | UDMASS_INTA0_GC_ECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmass_inta0_gc_ecc_pend |
1 | UDMASS_INTA0_MC_ECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmass_inta0_mc_ecc_pend |
0 | UDMASS_INTA0_LC_ECC_PEND | R/W1S | 0h | Interrupt Pending Status for udmass_inta0_lc_ecc_pend |
MCU_NAVSS_DED_STATUS_REG3 is shown in Figure 10-47 and described in Table 10-183.
Return to Summary Table.
Interrupt Status Register 3
Instance | Physical Address |
---|---|
MCU_NAVSS0_UDMASS_ECCAGGR0 | 2838 114Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_4_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_3_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_2_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_1_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_0_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_D_DEF_EVT_BRIDGE_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_DST_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_SRC_BUSECC_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_DST_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_SRC_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_2_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_1_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_0_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_DST_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_SRC_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_DST_BUSECC_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_SRC_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_DST_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_SRC_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_DST_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_SRC_BUSECC_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_2_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_1_PEND | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_0_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R/W | X | |
23 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_4_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_edc_ctrl_busecc_4_pend |
22 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_3_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_edc_ctrl_busecc_3_pend |
21 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_2_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_edc_ctrl_busecc_2_pend |
20 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_1_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_edc_ctrl_busecc_1_pend |
19 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_0_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_edc_ctrl_busecc_0_pend |
18 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_D_DEF_EVT_BRIDGE_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_d_def_evt_p2p_bridge_d_def_evt_bridge_busecc_pend |
17 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_DST_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_safeg_rt_pdma_mcu1_psil_d_etl0_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_etl0_bridge_dst_busecc_pend |
16 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_SRC_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_safeg_rt_pdma_mcu1_psil_d_etl0_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_etl0_bridge_src_busecc_pend |
15 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_DST_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_safeg_rt_pdma_mcu1_psil_s_etl0_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_etl0_bridge_dst_busecc_pend |
14 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_SRC_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_safeg_rt_pdma_mcu1_psil_s_etl0_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_etl0_bridge_src_busecc_pend |
13 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_2_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_edc_ctrl_busecc_2_pend |
12 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_1_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_edc_ctrl_busecc_1_pend |
11 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_0_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_edc_ctrl_busecc_0_pend |
10 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_DST_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_pdma_mcu1_psil_s_resp_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_resp_bridge_dst_busecc_pend |
9 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_SRC_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_pdma_mcu1_psil_s_resp_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_resp_bridge_src_busecc_pend |
8 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_DST_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_cpsw0_psil_s_resp_p2p_bridge_safeg_rt_cpsw0_psil_s_resp_bridge_dst_busecc_pend |
7 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_SRC_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_cpsw0_psil_s_resp_p2p_bridge_safeg_rt_cpsw0_psil_s_resp_bridge_src_busecc_pend |
6 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_DST_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_pdma_mcu1_psil_d_resp_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_resp_bridge_dst_busecc_pend |
5 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_SRC_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_pdma_mcu1_psil_d_resp_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_resp_bridge_src_busecc_pend |
4 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_DST_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_cpsw0_psil_d_resp_p2p_bridge_safeg_rt_cpsw0_psil_d_resp_bridge_dst_busecc_pend |
3 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_SRC_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_cpsw0_psil_d_resp_p2p_bridge_safeg_rt_cpsw0_psil_d_resp_bridge_src_busecc_pend |
2 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_2_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_edc_ctrl_busecc_2_pend |
1 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_1_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_edc_ctrl_busecc_1_pend |
0 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_0_PEND | R/W1S | 0h | Interrupt Pending Status for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_edc_ctrl_busecc_0_pend |
MCU_NAVSS_DED_ENABLE_SET_REG0 is shown in Figure 10-48 and described in Table 10-185.
Return to Summary Table.
Interrupt Enable Set Register 0
Instance | Physical Address |
---|---|
MCU_NAVSS0_UDMASS_ECCAGGR0 | 2838 1180h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
UDMAP0_RPCF1_RAMECC_ENABLE_SET | UDMAP0_RPCF0_RAMECC_ENABLE_SET | UDMAP0_RFFW_RAMECC_ENABLE_SET | UDMAP0_TPCF4_RAMECC_ENABLE_SET | UDMAP0_TPCF1_RAMECC_ENABLE_SET | UDMAP0_TPCF0_RAMECC_ENABLE_SET | UDMAP0_TSTATE_RAMECC_ENABLE_SET | UDMAP0_RPCU_CNTR_RAMECC_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
UDMAP0_RPCU_SB1_RAMECC_ENABLE_SET | UDMAP0_RPCU_SB0_RAMECC_ENABLE_SET | UDMAP0_RPTRCU_CNTR_RAMECC_ENABLE_SET | UDMAP0_RPTRSB2_RAMECC_ENABLE_SET | UDMAP0_RPTRSB1_RAMECC_ENABLE_SET | UDMAP0_RPTRSB0_RAMECC_ENABLE_SET | UDMAP0_TPTRCU_CNTR_RAMECC_ENABLE_SET | UDMAP0_TPTRSB2_RAMECC_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
UDMAP0_TPTRSB1_RAMECC_ENABLE_SET | UDMAP0_TPTRSB0_RAMECC_ENABLE_SET | UDMAP0_RPBUF_PF_RAMECC_ENABLE_SET | UDMAP0_RPBUF_DF_RAMECC_ENABLE_SET | UDMAP0_RPBUF_CF_RAMECC_ENABLE_SET | UDMAP0_RPRQ_RAMECC_ENABLE_SET | UDMAP0_RPCFG_RAMECC_ENABLE_SET | UDMAP0_RPSTATE_RAMECC_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UDMAP0_TPCU_CNTR_RAMECC_ENABLE_SET | UDMAP0_TPCU_RAMECC_ENABLE_SET | UDMAP0_TPBUF_PF_RAMECC_ENABLE_SET | UDMAP0_TPBUF_DF_RAMECC_ENABLE_SET | UDMAP0_TPBUF_CF_RAMECC_ENABLE_SET | UDMAP0_TPCFG_RAMECC_ENABLE_SET | UDMAP0_TPSTATE_RAMECC_ENABLE_SET | ECCAGG_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | UDMAP0_RPCF1_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rpcf1_ramecc_pend |
30 | UDMAP0_RPCF0_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rpcf0_ramecc_pend |
29 | UDMAP0_RFFW_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rffw_ramecc_pend |
28 | UDMAP0_TPCF4_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_tpcf4_ramecc_pend |
27 | UDMAP0_TPCF1_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_tpcf1_ramecc_pend |
26 | UDMAP0_TPCF0_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_tpcf0_ramecc_pend |
25 | UDMAP0_TSTATE_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_tstate_ramecc_pend |
24 | UDMAP0_RPCU_CNTR_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rpcu_cntr_ramecc_pend |
23 | UDMAP0_RPCU_SB1_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rpcu_sb1_ramecc_pend |
22 | UDMAP0_RPCU_SB0_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rpcu_sb0_ramecc_pend |
21 | UDMAP0_RPTRCU_CNTR_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rptrcu_cntr_ramecc_pend |
20 | UDMAP0_RPTRSB2_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rptrsb2_ramecc_pend |
19 | UDMAP0_RPTRSB1_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rptrsb1_ramecc_pend |
18 | UDMAP0_RPTRSB0_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rptrsb0_ramecc_pend |
17 | UDMAP0_TPTRCU_CNTR_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_tptrcu_cntr_ramecc_pend |
16 | UDMAP0_TPTRSB2_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_tptrsb2_ramecc_pend |
15 | UDMAP0_TPTRSB1_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_tptrsb1_ramecc_pend |
14 | UDMAP0_TPTRSB0_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_tptrsb0_ramecc_pend |
13 | UDMAP0_RPBUF_PF_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rpbuf_pf_ramecc_pend |
12 | UDMAP0_RPBUF_DF_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rpbuf_df_ramecc_pend |
11 | UDMAP0_RPBUF_CF_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rpbuf_cf_ramecc_pend |
10 | UDMAP0_RPRQ_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rprq_ramecc_pend |
9 | UDMAP0_RPCFG_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rpcfg_ramecc_pend |
8 | UDMAP0_RPSTATE_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rpstate_ramecc_pend |
7 | UDMAP0_TPCU_CNTR_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_tpcu_cntr_ramecc_pend |
6 | UDMAP0_TPCU_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_tpcu_ramecc_pend |
5 | UDMAP0_TPBUF_PF_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_tpbuf_pf_ramecc_pend |
4 | UDMAP0_TPBUF_DF_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_tpbuf_df_ramecc_pend |
3 | UDMAP0_TPBUF_CF_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_tpbuf_cf_ramecc_pend |
2 | UDMAP0_TPCFG_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_tpcfg_ramecc_pend |
1 | UDMAP0_TPSTATE_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_tpstate_ramecc_pend |
0 | ECCAGG_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for eccagg_pend |
MCU_NAVSS_DED_ENABLE_SET_REG1 is shown in Figure 10-49 and described in Table 10-187.
Return to Summary Table.
Interrupt Enable Set Register 1
Instance | Physical Address |
---|---|
MCU_NAVSS0_UDMASS_ECCAGGR0 | 2838 1184h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
UDMASS_INTA0_SR_ECC_ENABLE_SET | UDMASS_INTA0_IM_ECC_ENABLE_SET | NAVSS_MCU_UDMASS_UDMASS_INTA0_EDC_CTRL_BUSECC_ENABLE_SET | RINGACC0_ECC_ENABLE_SET | NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_1_ENABLE_SET | NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_0_ENABLE_SET | NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_2_ENABLE_SET | NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_1_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_0_ENABLE_SET | UDMAP0_RRNGOCC_RAMECC_ENABLE_SET | UDMAP0_TRNGOCC_RAMECC_ENABLE_SET | UDMAP0_PSILTID_RAMECC_ENABLE_SET | UDMAP0_PSILR_RAMECC_ENABLE_SET | UDMAP0_SDEC3_RAMECC_ENABLE_SET | UDMAP0_SDEC0_RAMECC_ENABLE_SET | UDMAP0_RDEC2_RAMECC_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
UDMAP0_RDEC1_RAMECC_ENABLE_SET | UDMAP0_RDEC0_RAMECC_ENABLE_SET | UDMAP0_REVTCNTR_RAMECC_ENABLE_SET | UDMAP0_TEVTCNTR_RAMECC_ENABLE_SET | UDMAP0_STS_RAMECC3_ENABLE_SET | UDMAP0_STS_RAMECC2_ENABLE_SET | UDMAP0_STS_RAMECC1_ENABLE_SET | UDMAP0_STS_RAMECC0_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UDMAP0_EH_RAMECC_ENABLE_SET | UDMAP0_PROXY_RAMECC_ENABLE_SET | UDMAP0_RSTATE_RAMECC_ENABLE_SET | UDMAP0_RFLOW1_RAMECC_ENABLE_SET | UDMAP0_RFLOW0_RAMECC_ENABLE_SET | UDMAP0_RPCF4_RAMECC_ENABLE_SET | UDMAP0_RPCF3_RAMECC_ENABLE_SET | UDMAP0_RPCF2_RAMECC_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | UDMASS_INTA0_SR_ECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmass_inta0_sr_ecc_pend |
30 | UDMASS_INTA0_IM_ECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmass_inta0_im_ecc_pend |
29 | NAVSS_MCU_UDMASS_UDMASS_INTA0_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_udmass_inta0_edc_ctrl_busecc_pend |
28 | RINGACC0_ECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ringacc0_ecc_pend |
27 | NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_1_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_1_pend |
26 | NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_0_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_0_pend |
25 | NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_2_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_2_pend |
24 | NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_1_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_1_pend |
23 | NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_0_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_0_pend |
22 | UDMAP0_RRNGOCC_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rrngocc_ramecc_pend |
21 | UDMAP0_TRNGOCC_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_trngocc_ramecc_pend |
20 | UDMAP0_PSILTID_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_psiltid_ramecc_pend |
19 | UDMAP0_PSILR_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_psilr_ramecc_pend |
18 | UDMAP0_SDEC3_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_sdec3_ramecc_pend |
17 | UDMAP0_SDEC0_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_sdec0_ramecc_pend |
16 | UDMAP0_RDEC2_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rdec2_ramecc_pend |
15 | UDMAP0_RDEC1_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rdec1_ramecc_pend |
14 | UDMAP0_RDEC0_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rdec0_ramecc_pend |
13 | UDMAP0_REVTCNTR_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_revtcntr_ramecc_pend |
12 | UDMAP0_TEVTCNTR_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_tevtcntr_ramecc_pend |
11 | UDMAP0_STS_RAMECC3_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_sts_ramecc3_pend |
10 | UDMAP0_STS_RAMECC2_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_sts_ramecc2_pend |
9 | UDMAP0_STS_RAMECC1_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_sts_ramecc1_pend |
8 | UDMAP0_STS_RAMECC0_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_sts_ramecc0_pend |
7 | UDMAP0_EH_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_eh_ramecc_pend |
6 | UDMAP0_PROXY_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_proxy_ramecc_pend |
5 | UDMAP0_RSTATE_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rstate_ramecc_pend |
4 | UDMAP0_RFLOW1_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rflow1_ramecc_pend |
3 | UDMAP0_RFLOW0_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rflow0_ramecc_pend |
2 | UDMAP0_RPCF4_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rpcf4_ramecc_pend |
1 | UDMAP0_RPCF3_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rpcf3_ramecc_pend |
0 | UDMAP0_RPCF2_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmap0_rpcf2_ramecc_pend |
MCU_NAVSS_DED_ENABLE_SET_REG2 is shown in Figure 10-50 and described in Table 10-189.
Return to Summary Table.
Interrupt Enable Set Register 2
Instance | Physical Address |
---|---|
MCU_NAVSS0_UDMASS_ECCAGGR0 | 2838 1188h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_DST_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_SRC_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_DST_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_SRC_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_DST_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_SRC_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_DST_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_SRC_BUSECC_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NAVSS_MCU_UDMASS_PSILSS0_CFG_NAVSS_MCU_UDMASS_PSILSS0_CFG_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_BUSECC_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_EDC_CTRL_BUSECC_ENABLE_SET | UDMASS_INTA0_GC_ECC_ENABLE_SET | UDMASS_INTA0_MC_ECC_ENABLE_SET | UDMASS_INTA0_LC_ECC_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_DST_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_pdma_mcu1_psil_d_data_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_data_bridge_dst_busecc_pend |
30 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_SRC_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_pdma_mcu1_psil_d_data_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_data_bridge_src_busecc_pend |
29 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_DST_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_cpsw0_psil_d_data_p2p_bridge_safeg_rt_cpsw0_psil_d_data_bridge_dst_busecc_pend |
28 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_SRC_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_cpsw0_psil_d_data_p2p_bridge_safeg_rt_cpsw0_psil_d_data_bridge_src_busecc_pend |
27 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_DST_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_pdma_mcu1_psil_s_data_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_data_bridge_dst_busecc_pend |
26 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_SRC_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_pdma_mcu1_psil_s_data_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_data_bridge_src_busecc_pend |
25 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_DST_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_cpsw0_psil_s_data_p2p_bridge_safeg_rt_cpsw0_psil_s_data_bridge_dst_busecc_pend |
24 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_SRC_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_cpsw0_psil_s_data_p2p_bridge_safeg_rt_cpsw0_psil_s_data_bridge_src_busecc_pend |
23 | NAVSS_MCU_UDMASS_PSILSS0_CFG_NAVSS_MCU_UDMASS_PSILSS0_CFG_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cfg_navss_mcu_udmass_psilss0_cfg_edc_ctrl_busecc_pend |
22 | NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_psilcfg0_cfgstrm_navss_mcu_udmass_psilss0_l2p_psilcfg0_cfgstrm_edc_ctrl_busecc_pend |
21 | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_udmap0_cfgstrm_navss_mcu_udmass_psilss0_l2p_udmap0_cfgstrm_edc_ctrl_busecc_pend |
20 | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_udmass_inta0_mevt_in_navss_mcu_udmass_psilss0_l2p_udmass_inta0_mevt_in_edc_ctrl_busecc_pend |
19 | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_udmass_inta0_cevt_navss_mcu_udmass_psilss0_l2p_udmass_inta0_cevt_edc_ctrl_busecc_pend |
18 | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_udmass_inta0_evt_navss_mcu_udmass_psilss0_l2p_udmass_inta0_evt_edc_ctrl_busecc_pend |
17 | NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_dmsc_evt_navss_mcu_udmass_psilss0_l2p_dmsc_evt_edc_ctrl_busecc_pend |
16 | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_udmap0_strm_navss_mcu_udmass_psilss0_l2p_udmap0_strm_edc_ctrl_busecc_pend |
15 | NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_pdma_mcu1_psil_navss_mcu_udmass_psilss0_l2p_pdma_mcu1_psil_edc_ctrl_busecc_pend |
14 | NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_pdma_mcu0_psil_navss_mcu_udmass_psilss0_l2p_pdma_mcu0_psil_edc_ctrl_busecc_pend |
13 | NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_cpsw0_psil_navss_mcu_udmass_psilss0_l2p_cpsw0_psil_edc_ctrl_busecc_pend |
12 | NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_navss_psil_navss_mcu_udmass_psilss0_l2p_navss_psil_edc_ctrl_busecc_pend |
11 | NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_psilcfg0_cfgstrm_bridge_navss_mcu_udmass_psilss0_psilcfg0_cfgstrm_bridge_edc_ctrl_busecc_pend |
10 | NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_udmap0_cfgstrm_bridge_navss_mcu_udmass_psilss0_udmap0_cfgstrm_bridge_edc_ctrl_busecc_pend |
9 | NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_psilcfg0_cfgstrm_safeg_navss_mcu_udmass_psilss0_psilcfg0_cfgstrm_safeg_edc_ctrl_busecc_pend |
8 | NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_udmap0_cfgstrm_safeg_navss_mcu_udmass_psilss0_udmap0_cfgstrm_safeg_edc_ctrl_busecc_pend |
7 | NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_udmap0_strm_safeg_navss_mcu_udmass_psilss0_udmap0_strm_safeg_edc_ctrl_busecc_pend |
6 | NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_pdma_mcu1_psil_safeg_navss_mcu_udmass_psilss0_pdma_mcu1_psil_safeg_edc_ctrl_busecc_pend |
5 | NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_pdma_mcu0_psil_safeg_navss_mcu_udmass_psilss0_pdma_mcu0_psil_safeg_edc_ctrl_busecc_pend |
4 | NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cpsw0_psil_safeg_navss_mcu_udmass_psilss0_cpsw0_psil_safeg_edc_ctrl_busecc_pend |
3 | NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_navss_psil_rt_bridge_navss_mcu_udmass_psilss0_navss_psil_rt_bridge_edc_ctrl_busecc_pend |
2 | UDMASS_INTA0_GC_ECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmass_inta0_gc_ecc_pend |
1 | UDMASS_INTA0_MC_ECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmass_inta0_mc_ecc_pend |
0 | UDMASS_INTA0_LC_ECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for udmass_inta0_lc_ecc_pend |
MCU_NAVSS_DED_ENABLE_SET_REG3 is shown in Figure 10-51 and described in Table 10-191.
Return to Summary Table.
Interrupt Enable Set Register 3
Instance | Physical Address |
---|---|
MCU_NAVSS0_UDMASS_ECCAGGR0 | 2838 118Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_D_DEF_EVT_BRIDGE_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_DST_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_SRC_BUSECC_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_DST_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_SRC_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_DST_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_SRC_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_DST_BUSECC_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_SRC_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_DST_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_SRC_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_DST_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_SRC_BUSECC_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R/W | X | |
23 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_edc_ctrl_busecc_4_pend |
22 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_edc_ctrl_busecc_3_pend |
21 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_edc_ctrl_busecc_2_pend |
20 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_edc_ctrl_busecc_1_pend |
19 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_edc_ctrl_busecc_0_pend |
18 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_D_DEF_EVT_BRIDGE_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_d_def_evt_p2p_bridge_d_def_evt_bridge_busecc_pend |
17 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_DST_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_safeg_rt_pdma_mcu1_psil_d_etl0_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_etl0_bridge_dst_busecc_pend |
16 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_SRC_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_safeg_rt_pdma_mcu1_psil_d_etl0_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_etl0_bridge_src_busecc_pend |
15 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_DST_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_safeg_rt_pdma_mcu1_psil_s_etl0_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_etl0_bridge_dst_busecc_pend |
14 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_SRC_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_safeg_rt_pdma_mcu1_psil_s_etl0_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_etl0_bridge_src_busecc_pend |
13 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_edc_ctrl_busecc_2_pend |
12 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_edc_ctrl_busecc_1_pend |
11 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_edc_ctrl_busecc_0_pend |
10 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_DST_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_pdma_mcu1_psil_s_resp_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_resp_bridge_dst_busecc_pend |
9 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_SRC_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_pdma_mcu1_psil_s_resp_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_resp_bridge_src_busecc_pend |
8 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_DST_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_cpsw0_psil_s_resp_p2p_bridge_safeg_rt_cpsw0_psil_s_resp_bridge_dst_busecc_pend |
7 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_SRC_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_cpsw0_psil_s_resp_p2p_bridge_safeg_rt_cpsw0_psil_s_resp_bridge_src_busecc_pend |
6 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_DST_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_pdma_mcu1_psil_d_resp_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_resp_bridge_dst_busecc_pend |
5 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_SRC_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_pdma_mcu1_psil_d_resp_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_resp_bridge_src_busecc_pend |
4 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_DST_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_cpsw0_psil_d_resp_p2p_bridge_safeg_rt_cpsw0_psil_d_resp_bridge_dst_busecc_pend |
3 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_SRC_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_cpsw0_psil_d_resp_p2p_bridge_safeg_rt_cpsw0_psil_d_resp_bridge_src_busecc_pend |
2 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_edc_ctrl_busecc_2_pend |
1 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_edc_ctrl_busecc_1_pend |
0 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_edc_ctrl_busecc_0_pend |
MCU_NAVSS_DED_ENABLE_CLR_REG0 is shown in Figure 10-52 and described in Table 10-193.
Return to Summary Table.
Interrupt Enable Clear Register 0
Instance | Physical Address |
---|---|
MCU_NAVSS0_UDMASS_ECCAGGR0 | 2838 11C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
UDMAP0_RPCF1_RAMECC_ENABLE_CLR | UDMAP0_RPCF0_RAMECC_ENABLE_CLR | UDMAP0_RFFW_RAMECC_ENABLE_CLR | UDMAP0_TPCF4_RAMECC_ENABLE_CLR | UDMAP0_TPCF1_RAMECC_ENABLE_CLR | UDMAP0_TPCF0_RAMECC_ENABLE_CLR | UDMAP0_TSTATE_RAMECC_ENABLE_CLR | UDMAP0_RPCU_CNTR_RAMECC_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
UDMAP0_RPCU_SB1_RAMECC_ENABLE_CLR | UDMAP0_RPCU_SB0_RAMECC_ENABLE_CLR | UDMAP0_RPTRCU_CNTR_RAMECC_ENABLE_CLR | UDMAP0_RPTRSB2_RAMECC_ENABLE_CLR | UDMAP0_RPTRSB1_RAMECC_ENABLE_CLR | UDMAP0_RPTRSB0_RAMECC_ENABLE_CLR | UDMAP0_TPTRCU_CNTR_RAMECC_ENABLE_CLR | UDMAP0_TPTRSB2_RAMECC_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
UDMAP0_TPTRSB1_RAMECC_ENABLE_CLR | UDMAP0_TPTRSB0_RAMECC_ENABLE_CLR | UDMAP0_RPBUF_PF_RAMECC_ENABLE_CLR | UDMAP0_RPBUF_DF_RAMECC_ENABLE_CLR | UDMAP0_RPBUF_CF_RAMECC_ENABLE_CLR | UDMAP0_RPRQ_RAMECC_ENABLE_CLR | UDMAP0_RPCFG_RAMECC_ENABLE_CLR | UDMAP0_RPSTATE_RAMECC_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UDMAP0_TPCU_CNTR_RAMECC_ENABLE_CLR | UDMAP0_TPCU_RAMECC_ENABLE_CLR | UDMAP0_TPBUF_PF_RAMECC_ENABLE_CLR | UDMAP0_TPBUF_DF_RAMECC_ENABLE_CLR | UDMAP0_TPBUF_CF_RAMECC_ENABLE_CLR | UDMAP0_TPCFG_RAMECC_ENABLE_CLR | UDMAP0_TPSTATE_RAMECC_ENABLE_CLR | ECCAGG_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | UDMAP0_RPCF1_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rpcf1_ramecc_pend |
30 | UDMAP0_RPCF0_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rpcf0_ramecc_pend |
29 | UDMAP0_RFFW_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rffw_ramecc_pend |
28 | UDMAP0_TPCF4_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_tpcf4_ramecc_pend |
27 | UDMAP0_TPCF1_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_tpcf1_ramecc_pend |
26 | UDMAP0_TPCF0_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_tpcf0_ramecc_pend |
25 | UDMAP0_TSTATE_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_tstate_ramecc_pend |
24 | UDMAP0_RPCU_CNTR_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rpcu_cntr_ramecc_pend |
23 | UDMAP0_RPCU_SB1_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rpcu_sb1_ramecc_pend |
22 | UDMAP0_RPCU_SB0_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rpcu_sb0_ramecc_pend |
21 | UDMAP0_RPTRCU_CNTR_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rptrcu_cntr_ramecc_pend |
20 | UDMAP0_RPTRSB2_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rptrsb2_ramecc_pend |
19 | UDMAP0_RPTRSB1_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rptrsb1_ramecc_pend |
18 | UDMAP0_RPTRSB0_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rptrsb0_ramecc_pend |
17 | UDMAP0_TPTRCU_CNTR_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_tptrcu_cntr_ramecc_pend |
16 | UDMAP0_TPTRSB2_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_tptrsb2_ramecc_pend |
15 | UDMAP0_TPTRSB1_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_tptrsb1_ramecc_pend |
14 | UDMAP0_TPTRSB0_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_tptrsb0_ramecc_pend |
13 | UDMAP0_RPBUF_PF_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rpbuf_pf_ramecc_pend |
12 | UDMAP0_RPBUF_DF_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rpbuf_df_ramecc_pend |
11 | UDMAP0_RPBUF_CF_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rpbuf_cf_ramecc_pend |
10 | UDMAP0_RPRQ_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rprq_ramecc_pend |
9 | UDMAP0_RPCFG_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rpcfg_ramecc_pend |
8 | UDMAP0_RPSTATE_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rpstate_ramecc_pend |
7 | UDMAP0_TPCU_CNTR_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_tpcu_cntr_ramecc_pend |
6 | UDMAP0_TPCU_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_tpcu_ramecc_pend |
5 | UDMAP0_TPBUF_PF_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_tpbuf_pf_ramecc_pend |
4 | UDMAP0_TPBUF_DF_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_tpbuf_df_ramecc_pend |
3 | UDMAP0_TPBUF_CF_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_tpbuf_cf_ramecc_pend |
2 | UDMAP0_TPCFG_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_tpcfg_ramecc_pend |
1 | UDMAP0_TPSTATE_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_tpstate_ramecc_pend |
0 | ECCAGG_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for eccagg_pend |
MCU_NAVSS_DED_ENABLE_CLR_REG1 is shown in Figure 10-53 and described in Table 10-195.
Return to Summary Table.
Interrupt Enable Clear Register 1
Instance | Physical Address |
---|---|
MCU_NAVSS0_UDMASS_ECCAGGR0 | 2838 11C4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
UDMASS_INTA0_SR_ECC_ENABLE_CLR | UDMASS_INTA0_IM_ECC_ENABLE_CLR | NAVSS_MCU_UDMASS_UDMASS_INTA0_EDC_CTRL_BUSECC_ENABLE_CLR | RINGACC0_ECC_ENABLE_CLR | NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_1_ENABLE_CLR | NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_0_ENABLE_CLR | NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_2_ENABLE_CLR | NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_1_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_0_ENABLE_CLR | UDMAP0_RRNGOCC_RAMECC_ENABLE_CLR | UDMAP0_TRNGOCC_RAMECC_ENABLE_CLR | UDMAP0_PSILTID_RAMECC_ENABLE_CLR | UDMAP0_PSILR_RAMECC_ENABLE_CLR | UDMAP0_SDEC3_RAMECC_ENABLE_CLR | UDMAP0_SDEC0_RAMECC_ENABLE_CLR | UDMAP0_RDEC2_RAMECC_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
UDMAP0_RDEC1_RAMECC_ENABLE_CLR | UDMAP0_RDEC0_RAMECC_ENABLE_CLR | UDMAP0_REVTCNTR_RAMECC_ENABLE_CLR | UDMAP0_TEVTCNTR_RAMECC_ENABLE_CLR | UDMAP0_STS_RAMECC3_ENABLE_CLR | UDMAP0_STS_RAMECC2_ENABLE_CLR | UDMAP0_STS_RAMECC1_ENABLE_CLR | UDMAP0_STS_RAMECC0_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UDMAP0_EH_RAMECC_ENABLE_CLR | UDMAP0_PROXY_RAMECC_ENABLE_CLR | UDMAP0_RSTATE_RAMECC_ENABLE_CLR | UDMAP0_RFLOW1_RAMECC_ENABLE_CLR | UDMAP0_RFLOW0_RAMECC_ENABLE_CLR | UDMAP0_RPCF4_RAMECC_ENABLE_CLR | UDMAP0_RPCF3_RAMECC_ENABLE_CLR | UDMAP0_RPCF2_RAMECC_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | UDMASS_INTA0_SR_ECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmass_inta0_sr_ecc_pend |
30 | UDMASS_INTA0_IM_ECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmass_inta0_im_ecc_pend |
29 | NAVSS_MCU_UDMASS_UDMASS_INTA0_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_udmass_inta0_edc_ctrl_busecc_pend |
28 | RINGACC0_ECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ringacc0_ecc_pend |
27 | NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_1_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_1_pend |
26 | NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_0_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_0_pend |
25 | NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_2_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_2_pend |
24 | NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_1_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_1_pend |
23 | NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_0_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_0_pend |
22 | UDMAP0_RRNGOCC_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rrngocc_ramecc_pend |
21 | UDMAP0_TRNGOCC_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_trngocc_ramecc_pend |
20 | UDMAP0_PSILTID_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_psiltid_ramecc_pend |
19 | UDMAP0_PSILR_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_psilr_ramecc_pend |
18 | UDMAP0_SDEC3_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_sdec3_ramecc_pend |
17 | UDMAP0_SDEC0_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_sdec0_ramecc_pend |
16 | UDMAP0_RDEC2_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rdec2_ramecc_pend |
15 | UDMAP0_RDEC1_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rdec1_ramecc_pend |
14 | UDMAP0_RDEC0_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rdec0_ramecc_pend |
13 | UDMAP0_REVTCNTR_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_revtcntr_ramecc_pend |
12 | UDMAP0_TEVTCNTR_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_tevtcntr_ramecc_pend |
11 | UDMAP0_STS_RAMECC3_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_sts_ramecc3_pend |
10 | UDMAP0_STS_RAMECC2_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_sts_ramecc2_pend |
9 | UDMAP0_STS_RAMECC1_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_sts_ramecc1_pend |
8 | UDMAP0_STS_RAMECC0_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_sts_ramecc0_pend |
7 | UDMAP0_EH_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_eh_ramecc_pend |
6 | UDMAP0_PROXY_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_proxy_ramecc_pend |
5 | UDMAP0_RSTATE_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rstate_ramecc_pend |
4 | UDMAP0_RFLOW1_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rflow1_ramecc_pend |
3 | UDMAP0_RFLOW0_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rflow0_ramecc_pend |
2 | UDMAP0_RPCF4_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rpcf4_ramecc_pend |
1 | UDMAP0_RPCF3_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rpcf3_ramecc_pend |
0 | UDMAP0_RPCF2_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmap0_rpcf2_ramecc_pend |
MCU_NAVSS_DED_ENABLE_CLR_REG2 is shown in Figure 10-54 and described in Table 10-197.
Return to Summary Table.
Interrupt Enable Clear Register 2
Instance | Physical Address |
---|---|
MCU_NAVSS0_UDMASS_ECCAGGR0 | 2838 11C8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_DST_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_SRC_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_DST_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_SRC_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_DST_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_SRC_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_DST_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_SRC_BUSECC_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NAVSS_MCU_UDMASS_PSILSS0_CFG_NAVSS_MCU_UDMASS_PSILSS0_CFG_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_BUSECC_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_EDC_CTRL_BUSECC_ENABLE_CLR | UDMASS_INTA0_GC_ECC_ENABLE_CLR | UDMASS_INTA0_MC_ECC_ENABLE_CLR | UDMASS_INTA0_LC_ECC_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_DST_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_pdma_mcu1_psil_d_data_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_data_bridge_dst_busecc_pend |
30 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_SRC_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_pdma_mcu1_psil_d_data_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_data_bridge_src_busecc_pend |
29 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_DST_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_cpsw0_psil_d_data_p2p_bridge_safeg_rt_cpsw0_psil_d_data_bridge_dst_busecc_pend |
28 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_SRC_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_cpsw0_psil_d_data_p2p_bridge_safeg_rt_cpsw0_psil_d_data_bridge_src_busecc_pend |
27 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_DST_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_pdma_mcu1_psil_s_data_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_data_bridge_dst_busecc_pend |
26 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_SRC_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_pdma_mcu1_psil_s_data_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_data_bridge_src_busecc_pend |
25 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_DST_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_cpsw0_psil_s_data_p2p_bridge_safeg_rt_cpsw0_psil_s_data_bridge_dst_busecc_pend |
24 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_SRC_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_safeg_rt_cpsw0_psil_s_data_p2p_bridge_safeg_rt_cpsw0_psil_s_data_bridge_src_busecc_pend |
23 | NAVSS_MCU_UDMASS_PSILSS0_CFG_NAVSS_MCU_UDMASS_PSILSS0_CFG_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cfg_navss_mcu_udmass_psilss0_cfg_edc_ctrl_busecc_pend |
22 | NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_psilcfg0_cfgstrm_navss_mcu_udmass_psilss0_l2p_psilcfg0_cfgstrm_edc_ctrl_busecc_pend |
21 | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_udmap0_cfgstrm_navss_mcu_udmass_psilss0_l2p_udmap0_cfgstrm_edc_ctrl_busecc_pend |
20 | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_udmass_inta0_mevt_in_navss_mcu_udmass_psilss0_l2p_udmass_inta0_mevt_in_edc_ctrl_busecc_pend |
19 | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_udmass_inta0_cevt_navss_mcu_udmass_psilss0_l2p_udmass_inta0_cevt_edc_ctrl_busecc_pend |
18 | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_udmass_inta0_evt_navss_mcu_udmass_psilss0_l2p_udmass_inta0_evt_edc_ctrl_busecc_pend |
17 | NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_dmsc_evt_navss_mcu_udmass_psilss0_l2p_dmsc_evt_edc_ctrl_busecc_pend |
16 | NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_udmap0_strm_navss_mcu_udmass_psilss0_l2p_udmap0_strm_edc_ctrl_busecc_pend |
15 | NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_pdma_mcu1_psil_navss_mcu_udmass_psilss0_l2p_pdma_mcu1_psil_edc_ctrl_busecc_pend |
14 | NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_pdma_mcu0_psil_navss_mcu_udmass_psilss0_l2p_pdma_mcu0_psil_edc_ctrl_busecc_pend |
13 | NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_cpsw0_psil_navss_mcu_udmass_psilss0_l2p_cpsw0_psil_edc_ctrl_busecc_pend |
12 | NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_navss_psil_navss_mcu_udmass_psilss0_l2p_navss_psil_edc_ctrl_busecc_pend |
11 | NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_psilcfg0_cfgstrm_bridge_navss_mcu_udmass_psilss0_psilcfg0_cfgstrm_bridge_edc_ctrl_busecc_pend |
10 | NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_udmap0_cfgstrm_bridge_navss_mcu_udmass_psilss0_udmap0_cfgstrm_bridge_edc_ctrl_busecc_pend |
9 | NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_psilcfg0_cfgstrm_safeg_navss_mcu_udmass_psilss0_psilcfg0_cfgstrm_safeg_edc_ctrl_busecc_pend |
8 | NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_udmap0_cfgstrm_safeg_navss_mcu_udmass_psilss0_udmap0_cfgstrm_safeg_edc_ctrl_busecc_pend |
7 | NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_udmap0_strm_safeg_navss_mcu_udmass_psilss0_udmap0_strm_safeg_edc_ctrl_busecc_pend |
6 | NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_pdma_mcu1_psil_safeg_navss_mcu_udmass_psilss0_pdma_mcu1_psil_safeg_edc_ctrl_busecc_pend |
5 | NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_pdma_mcu0_psil_safeg_navss_mcu_udmass_psilss0_pdma_mcu0_psil_safeg_edc_ctrl_busecc_pend |
4 | NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cpsw0_psil_safeg_navss_mcu_udmass_psilss0_cpsw0_psil_safeg_edc_ctrl_busecc_pend |
3 | NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_navss_psil_rt_bridge_navss_mcu_udmass_psilss0_navss_psil_rt_bridge_edc_ctrl_busecc_pend |
2 | UDMASS_INTA0_GC_ECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmass_inta0_gc_ecc_pend |
1 | UDMASS_INTA0_MC_ECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmass_inta0_mc_ecc_pend |
0 | UDMASS_INTA0_LC_ECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for udmass_inta0_lc_ecc_pend |
MCU_NAVSS_DED_ENABLE_CLR_REG3 is shown in Figure 10-55 and described in Table 10-199.
Return to Summary Table.
Interrupt Enable Clear Register 3
Instance | Physical Address |
---|---|
MCU_NAVSS0_UDMASS_ECCAGGR0 | 2838 11CCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_D_DEF_EVT_BRIDGE_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_DST_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_SRC_BUSECC_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_DST_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_SRC_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_DST_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_SRC_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_DST_BUSECC_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_SRC_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_DST_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_SRC_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_DST_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_SRC_BUSECC_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R/W | X | |
23 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_edc_ctrl_busecc_4_pend |
22 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_edc_ctrl_busecc_3_pend |
21 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_edc_ctrl_busecc_2_pend |
20 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_edc_ctrl_busecc_1_pend |
19 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_navss_mcu_udmass_psilss0_cbass_etl_scr3_scr_edc_ctrl_busecc_0_pend |
18 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_D_DEF_EVT_BRIDGE_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_d_def_evt_p2p_bridge_d_def_evt_bridge_busecc_pend |
17 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_DST_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_safeg_rt_pdma_mcu1_psil_d_etl0_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_etl0_bridge_dst_busecc_pend |
16 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_SRC_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_safeg_rt_pdma_mcu1_psil_d_etl0_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_etl0_bridge_src_busecc_pend |
15 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_DST_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_safeg_rt_pdma_mcu1_psil_s_etl0_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_etl0_bridge_dst_busecc_pend |
14 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_SRC_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_etl_navss_mcu_udmass_psilss0_cbass_etl_safeg_rt_pdma_mcu1_psil_s_etl0_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_etl0_bridge_src_busecc_pend |
13 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_edc_ctrl_busecc_2_pend |
12 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_edc_ctrl_busecc_1_pend |
11 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_navss_mcu_udmass_psilss0_cbass_resp_scr2_scr_edc_ctrl_busecc_0_pend |
10 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_DST_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_pdma_mcu1_psil_s_resp_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_resp_bridge_dst_busecc_pend |
9 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_SRC_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_pdma_mcu1_psil_s_resp_p2p_bridge_safeg_rt_pdma_mcu1_psil_s_resp_bridge_src_busecc_pend |
8 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_DST_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_cpsw0_psil_s_resp_p2p_bridge_safeg_rt_cpsw0_psil_s_resp_bridge_dst_busecc_pend |
7 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_SRC_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_cpsw0_psil_s_resp_p2p_bridge_safeg_rt_cpsw0_psil_s_resp_bridge_src_busecc_pend |
6 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_DST_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_pdma_mcu1_psil_d_resp_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_resp_bridge_dst_busecc_pend |
5 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_SRC_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_pdma_mcu1_psil_d_resp_p2p_bridge_safeg_rt_pdma_mcu1_psil_d_resp_bridge_src_busecc_pend |
4 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_DST_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_cpsw0_psil_d_resp_p2p_bridge_safeg_rt_cpsw0_psil_d_resp_bridge_dst_busecc_pend |
3 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_SRC_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_resp_navss_mcu_udmass_psilss0_cbass_resp_safeg_rt_cpsw0_psil_d_resp_p2p_bridge_safeg_rt_cpsw0_psil_d_resp_bridge_src_busecc_pend |
2 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_edc_ctrl_busecc_2_pend |
1 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_edc_ctrl_busecc_1_pend |
0 | NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cbass_data_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_navss_mcu_udmass_psilss0_cbass_data_scr1_scr_edc_ctrl_busecc_0_pend |
MCU_NAVSS_AGGR_ENABLE_SET is shown in Figure 10-56 and described in Table 10-201.
Return to Summary Table.
AGGR interrupt enable set Register
Instance | Physical Address |
---|---|
MCU_NAVSS0_UDMASS_ECCAGGR0 | 2838 1200h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R/W-X | R/W1S-0h | R/W1S-0h | |||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1 | TIMEOUT | R/W1S | 0h | interrupt enable set for svbus timeout errors |
0 | PARITY | R/W1S | 0h | interrupt enable set for parity errors |
MCU_NAVSS_AGGR_ENABLE_CLR is shown in Figure 10-57 and described in Table 10-203.
Return to Summary Table.
AGGR interrupt enable clear Register
Instance | Physical Address |
---|---|
MCU_NAVSS0_UDMASS_ECCAGGR0 | 2838 1204h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R/W-X | R/W1C-0h | R/W1C-0h | |||||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1 | TIMEOUT | R/W1C | 0h | interrupt enable clear for svbus timeout errors |
0 | PARITY | R/W1C | 0h | interrupt enable clear for parity errors |
MCU_NAVSS_AGGR_STATUS_SET is shown in Figure 10-58 and described in Table 10-205.
Return to Summary Table.
AGGR interrupt status set Register
Instance | Physical Address |
---|---|
MCU_NAVSS0_UDMASS_ECCAGGR0 | 2838 1208h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R/W-X | R/Wincr-0h | R/Wincr-0h | |||||
LEGEND: R/W = Read/Write; R/Wincr = Read/Write to Increment Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | X | |
3-2 | TIMEOUT | R/Wincr | 0h | interrupt status set for svbus timeout errors |
1-0 | PARITY | R/Wincr | 0h | interrupt status set for parity errors |
MCU_NAVSS_AGGR_STATUS_CLR is shown in Figure 10-59 and described in Table 10-207.
Return to Summary Table.
AGGR interrupt status clear Register
Instance | Physical Address |
---|---|
MCU_NAVSS0_UDMASS_ECCAGGR0 | 2838 120Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R/W-X | R/Wdecr-0h | R/Wdecr-0h | |||||
LEGEND: R/W = Read/Write; R/Wdecr = Read/Write to Decrement Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | X | |
3-2 | TIMEOUT | R/Wdecr | 0h | interrupt status clear for svbus timeout errors |
1-0 | PARITY | R/Wdecr | 0h | interrupt status clear for parity errors |