SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Table 6-522 through Table 6-524 lists the memory-mapped registers for the PRU_ICSSG PRU_DEBUG, RTU_PRU_DEBUG and TX_PRU_DEBUG. All register offset addresses not listed in Table 6-522 through Table 6-524 should be considered as reserved locations and the register contents should not be modified.
PDSP in instance names is equivalent to the PRU processor names.
Instance | Base Address |
---|---|
PRU_ICSSG0_PR1_PDSP0_IRAM_DEBUG | 3002 2400h |
PRU_ICSSG0_PR1_PDSP1_IRAM_DEBUG | 3002 4400h |
PRU_ICSSG1_PR1_PDSP0_IRAM_DEBUG | 300A 2400h |
PRU_ICSSG1_PR1_PDSP1_IRAM_DEBUG | 300A 4400h |
PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_DEBUG | 3002 3400h |
PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_DEBUG | 3002 3C00h |
PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_DEBUG | 300A 3400h |
PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_DEBUG | 300A 3C00h |
PRU_ICSSG0_PR1_TX_PDSP0_IRAM_DEBUG | 3002 5400h |
PRU_ICSSG0_PR1_TX_PDSP1_IRAM_DEBUG | 3002 5C00h |
PRU_ICSSG1_PR1_TX_PDSP0_IRAM_DEBUG | 300A 5400h |
PRU_ICSSG1_PR1_TX_PDSP1_IRAM_DEBUG | 300A 5C00h |
Offset | Acronym | Register Name | PRU_ICSSG0_PR1_PDSP0_IRAM_DEBUG Physical Address | PRU_ICSSG0_PR1_PDSP1_IRAM_DEBUG Physical Address | PRU_ICSSG1_PR1_PDSP0_IRAM_DEBUG Physical Address | PRU_ICSSG1_PR1_PDSP1_IRAM_DEBUG Physical Address |
---|---|---|---|---|---|---|
0h + formula | ICSSG_DBG_GPREG_y | DEBUG PRU General Purpose Registers 0 to 31 | 3002 2400h + formula | 3002 4400h + formula | 300A 2400h + formula | 300A 4400h + formula |
80h + formula | ICSSG_DBG_CT_REG_y | DEBUG PRU Constant Table Entry Registers 0 to 31 | 3002 2480h + formula | 3002 4480h + formula | 300A 2480h + formula | 300A 4480h + formula |
Offset | Acronym | Register Name | PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_DEBUG Physical Address | PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_DEBUG Physical Address | PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_DEBUG Physical Address | PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_DEBUG Physical Address |
---|---|---|---|---|---|---|
0h + formula | ICSSG_DBG_GPREG_y | DEBUG PRU General Purpose Registers 0 to 31 | 3002 3400h + formula | 3002 3C00h + formula | 300A 3400h + formula | 300A 3C00h + formula |
80h + formula | ICSSG_DBG_CT_REG_y | DEBUG PRU Constant Table Entry Registers 0 to 31 | 3002 3480h + formula | 3002 3C80h + formula | 300A 3480h + formula | 300A 3C80h + formula |
Offset | Acronym | Register Name | PRU_ICSSG0_PR1_TX_PDSP0_IRAM_DEBUG Physical Address | PRU_ICSSG0_PR1_TX_PDSP1_IRAM_DEBUG Physical Address | PRU_ICSSG1_PR1_TX_PDSP0_IRAM_DEBUG Physical Address | PRU_ICSSG1_PR1_TX_PDSP1_IRAM_DEBUG Physical Address |
---|---|---|---|---|---|---|
0h + formula | ICSSG_DBG_GPREG_y | DEBUG PRU General Purpose Registers 0 to 31 | 3002 5400h + formula | 3002 5C00h + formula | 300A 5400h + formula | 300A 5C00h + formula |
80h + formula | ICSSG_DBG_CT_REG_y | DEBUG PRU Constant Table Entry Registers 0 to 31 | 3002 5480h + formula | 3002 5C80h + formula | 300A 5480h + formula | 300A 5C80h + formula |
ICSSG_DBG_GPREG_y is shown in Figure 6-278 and described in Table 6-526.
Return to Summary Table.
DEBUG PRU General Purpose Registers 0 to 31. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written.
Offset = 0h + (y * 4); where y = 0 to 31
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_PDSP0_IRAM_DEBUG | 3002 2400h + formula |
PRU_ICSSG0_PR1_PDSP1_IRAM_DEBUG | 3002 4400h + formula |
PRU_ICSSG1_PR1_PDSP0_IRAM_DEBUG | 300A 2400h + formula |
PRU_ICSSG1_PR1_PDSP1_IRAM_DEBUG | 300A 4400h + formula |
PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_DEBUG | 3002 3400h + formula |
PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_DEBUG | 3002 3C00h + formula |
PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_DEBUG | 300A 3400h + formula |
PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_DEBUG | 300A 3C00h + formula |
PRU_ICSSG0_PR1_TX_PDSP0_IRAM_DEBUG | 3002 5400h + formula |
PRU_ICSSG0_PR1_TX_PDSP1_IRAM_DEBUG | 3002 5C00h + formula |
PRU_ICSSG1_PR1_TX_PDSP0_IRAM_DEBUG | 300A 5400h + formula |
PRU_ICSSG1_PR1_TX_PDSP1_IRAM_DEBUG | 300A 5C00h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GP_REGy | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | GP_REGy | R/W | 0h | PRU Internal GP Register y: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal register file. |
ICSSG_DBG_CT_REG_y is shown in Figure 6-279 and described in Table 6-528.
Return to Summary Table.
DEBUG PRU Constant Table Entry Registers 0 to 31. This register allows an external agent to debug/or configure the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table.
Offset = 80h + (y * 4); where y = 0 to 31
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_PDSP0_IRAM_DEBUG | 3002 2480h + formula |
PRU_ICSSG0_PR1_PDSP1_IRAM_DEBUG | 3002 4480h + formula |
PRU_ICSSG1_PR1_PDSP0_IRAM_DEBUG | 300A 2480h + formula |
PRU_ICSSG1_PR1_PDSP1_IRAM_DEBUG | 300A 4480h + formula |
PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_DEBUG | 3002 3480h + formula |
PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_DEBUG | 3002 3C80h + formula |
PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_DEBUG | 300A 3480h + formula |
PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_DEBUG | 300A 3C80h + formula |
PRU_ICSSG0_PR1_TX_PDSP0_IRAM_DEBUG | 3002 5480h + formula |
PRU_ICSSG0_PR1_TX_PDSP1_IRAM_DEBUG | 3002 5C80h + formula |
PRU_ICSSG1_PR1_TX_PDSP0_IRAM_DEBUG | 300A 5480h + formula |
PRU_ICSSG1_PR1_TX_PDSP1_IRAM_DEBUG | 300A 5C80h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CT_REGy | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CT_REGy | R/W | 0h | PRU Internal Constants Table Entry y (where y = 0 to 31): Reading this field directly inspects the corresponding entry in the PRU internal constants table. Note: For each register y where y is less than the ctreg_cnt configuration parameter, the PRU internal Constants Table Entry Register will be writable and these registers are to be used to set the value for these constants. As for reads, the PRU must be disabled in order to access these registers. |