The PRU_ICSSG subsystem includes the
following main features:
- Two 32-bit load/store RISC CPU
cores — Programmable Real-Time Units (PRU0 and PRU1), each with:
- 20 Enhanced
General-Purpose Inputs (EGPI) and 20 Enhanced General-Purpose Outputs
(EGPO)
- Asynchronous capture
[Serial Capture Unit (SCU)] with EnDat 2.2 protocol and Sigma-Delta
demodulation support
- 12KB program memory per
PRU (PRU0_IRAM and PRU1_IRAM) with ECC
- 2KB Broadside (BS)
RAM
- MAC (Multiplier with
optional Accumulation)
- CRC16/CRC32 hardware
accelerator
- Byte Swap, for Little/Big
Endian conversion
- SUM32 Hardware
accelerator for UDP checksum
- Task Manager (Preemption
support)
- Broadside (32 Byte)
connection to MII_G_RTn (where n = 1 or 2), Filter Data Base (FDB), IPC
SPAD Memory, Scratchpad Memory (SPAD), SPINLOCK, XFR2VBUS, RTU_PRUm and
TX_PRUm (where m = 0 or 1)
- Two auxiliary Real-Time Transfer
Units (RTU_PRU0 and RTU_PRU1), each with:
- 8KB program memory with
ECC
- 2KB Broadside (BS)
RAM
- MAC (Multiplier with
optional Accumulation)
- CRC16/CRC32 Hardware
accelerator
- Byte Swap, for Little/Big
Endian conversion
- SUM32 Hardware
accelerator for UDP checksum
- Task Manager (Preemption
support)
- XFR2TR, for accelerating
the internal memory copy of worklist from TRs (Transfer Requests)
- Broadside (32 Byte)
connection to MII_G_RTn (where n = 1 or 2), Filter Data Base (FDB), IPC
SPAD Memory, Scratchpad Memory (SPAD), SPINLOCK, XFR2VBUS, PRUm and
TX_PRUm (where m = 0 or 1)
- Two Transmit Real-Time Transfer
Units (TX_PRU0 and TX_PRU1), each with:
- 6KB program memory with
ECC
- 2KB Broadside (BS)
RAM
- MAC (Multiplier with
optional Accumulation)
- CRC16/CRC32 Hardware
accelerator
- Byte Swap, for Little/Big
Endian conversion
- Task Manager (Preemption
support)
- Broadside (32 Byte)
connection to the TX L2 FIFO of MII_G_RTn port (where n = 1 or 2),
TX_PRU Scratchpad Memory (SPAD), SPINLOCK, XFR2VBUS, PRUm and RTU_PRUm
(where m= 0 or 1)
- Scratchpad Memory (SPAD) with 8
banks of 30 × 32-bit registers:
- 3 banks for the PRU0 and
PRU1 cores
- 3 banks for the RTU_PRU0
and RTU_PRU1 cores
- 2 banks for the TX_PRU0
and TX_PRU1 cores
- 64 KB Shared general purpose
memory RAM with ECC (Data RAM2), shared between PRU0 and PRU1
- Two 8 KB (shared) Data Memories
with ECC (Data RAM0 and Data RAM1)
- 64-bit VBUSM Controller Port:
- Optional address
translation for all transactions to External Host
- 16 Software Events generated by 2
PRUs
- Two Real-Time Ethernet ports
(MII_G_RT1 and MII_G_RT2) configurable to connect to each PRUn (where n = 0 or
1) to support multiple industrial communication protocols.
- Each of the Ethernet
ports can be configured as MII/RGMII/SGMII ports
- NOTE: SGMII mode is not
supported in this device.
- RX Classifier per
port
- Two Industrial Ethernet
Peripheral's (IEP0/IEP1) to manage/generate Industrial Ethernet functions such
as time stamping.
- Each of the Industrial
Ethernet 64-bit timers support 10 capture and 16 compare events along
with slow and fast compensation.
- Supports up to 4 sets of
3-phased motor control with 12 primary and 12 complimentary programmable
PWM outputs.
- Up to 9 safety events
with optional external trip IO per PWM set with hardware glitch
filter.
- One MDIO port to control external
Ethernet PHY
- One Enhanced Capture Module
(ECAP0)
- 16550-compatible UART with a
dedicated 192-MHz clock to support 12-Mbps PROFIBUS
- Interrupt Controller (INTC)
- Up to 64 internal events,
generated by modules, internal to the PRU_ICSSG
- Up to 96 external events,
generated by the system
- Supports up to 20
interrupt channels
- Generation of 20 Host
interrupts:
- 2 Host interrupts
to PRU0, PRU1, TX_PRU0 and TX_PRU1
- 2 Host interrupts
to RTU_PRU0 and RTU_PRU1
- 8 Host
interrupts, exported from the PRU_ICSSG for signaling the Arm
interrupt controllers (pulse and level provided)
- 8 Host Interrupts
for the Task Managers
- Each system event can be
enabled and disabled
- Each host event can be
enabled and disabled
- Hardware prioritization
of events
- One 32-bit VBUSP target port for
memory mapped register and internal memories access
- Flexible power management
support
- Integrated 32-bit
Interconnect