SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Table 9-7 and Table 9-8 show the Arm GIC-500 memory regions.
Instance | Base Address |
---|---|
Distributor registers (GICD_*) | 0180 0000h |
Distributor registers for message-based SPIs (GICD_*) | 0181 0000h |
ITS translation service control registers (GITS_*) | 0182 0000h |
Redistributor registers for control and physical LPIs for A53 core 0 (GICR_*) | 0184 0000h |
Redistributor registers for SGIs and PPis for A53 core 0 (GICR_*) | 0185 0000h |
Redistributor registers for control and physical LPIs for A53 core 1 (GICR_*) | 0186 0000h |
Redistributor registers for SGIs and PPis for A53 core 1 (GICR_*) | 0187 0000h |
Instance | Base Address |
---|---|
GICSS0_GIC_TRANSLATER(1) | 0100 0000h |
According to the Arm GIC-500 TRM, the GITS_TRANSLATER region is supposed to start at offset 30000h in the Arm GIC-500 address map. However, because the SoC implementation uses address-based method of accessing the GITS_TRANSLATER, it is accessed through a SoC assigned address and not through the 30000h offset defined in the Arm GIC-500 TRM.
For detailed Arm GIC-500 register map and register descriptions, refer to the Arm® CoreLink™ GIC-500 Generic Interrupt Controller Technical Reference Manual.