SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
This device supports an Arm® CoreSight™ compliant four-channel programmable on-chip Cross Triggering network. In addition to the four-channel on-chip network, this device implements two channels of product level triggering via the EMU0 and EMU1 device pins.
Conceptually, each channel of Cross Triggering can be viewed as mapping of a user-defined set of events to a user-defined set of actions, where the occurrence of any event in the set-of-events results in the generation of the set-of-actions. Table 13-7 provides a domain-level summary of the supported events and actions.
Domain | Events | Actions |
---|---|---|
Product-Level | Zero detected on EMU0 input pin | EMU0 output pin driven to Zero |
Zero detected on EMU1 input pin | EMU1 output pin driven to Zero | |
SoC Debug | TBR Acquisition Complete | TPIU insert trigger packet |
TBR Embedded buffer is full | TPIU start flush process | |
System reset asserted | TBR insert trigger packet | |
Bus Probe-n match | TBR start flush process | |
STM write to a TRIG location | Bus Probe-n Start | |
STM write to a trigger-enabled stimulus port | Bus Probe-n Stop | |
DMSC0 | DMSC_M3 has halted | DMSC_M3 - halt request |
DMSC_M3 - resume request | ||
MCU_M4F | MCU_M4F has halted | MCU_M4F – halt request |
ETM External Out (EXTOUT) trigger | MCU_M4F – resume request | |
-- | ETM External In (EXTIN) trigger | |
R5FFS0, R5FFS1 | R5FFS# core-n has halted | R5FFS# core-n – halt request |
PMU generated interrupt | R5FFS# core-n – resume request | |
ETM External Out (EXTOUT) trigger | ETM External In (EXTIN) trigger | |
A53SS0 | A53SS0 core-n has halted | A53SS0 core-n – halt request |
PMU generated interrupt | A53SS0 core-n – resume request | |
ETM External Out (EXTOUT) trigger | CTI interrupt | |
-- | ETM External In (EXTIN) trigger |